1 / 21

Lecture #38: Memory (2)

Lecture #38: Memory (2). Last lecture: Memory Architecture Static Ram This lecture Dynamic Ram E 2 memory. Word Line. C. . . . Bit Line. Sense Amp. DRAM Operations. Write Charge bitline HIGH or LOW and set wordline HIGH Read

zaviera
Download Presentation

Lecture #38: Memory (2)

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Lecture #38: Memory (2) • Last lecture: • Memory Architecture • Static Ram • This lecture • Dynamic Ram • E2 memory EE 42 fall 2004 lecture 38

  2. Word Line C ... Bit Line Sense Amp DRAM Operations • Write • Charge bitline HIGH or LOW and set wordline HIGH • Read • Bit line is precharged to a voltage halfway between HIGH and LOW, and then the word line is set HIGH. • Depending on the charge in the cap, the precharged bitline is pulled slightly higheror lower. • Sense Amp Detects change • The signal is decreased by the ratio of the storage capacitance to the bitline capacitance • Increase density => increase parasiticcapacitance • As geometries shrink, still need large bit capacitance EE 42 fall 2004 lecture 38

  3. DRAM logical organization D Column Decoder … Sense Amps & I/O 1 1 Q Row decoder Control logic Memory Array A0…A1 0 … Select Write enable EE 42 fall 2004 lecture 38

  4. DRAM sense amp +V Both precharged to ½ V Bit line Data out EE 42 fall 2004 lecture 38

  5. DRAM sense amplifier • The reason that DRAM is slow, is that a very small charge is captured on the capacitor, and the small voltage change on the line must be sensed. V Charge dumped to bit line Sense amp decides 0 or 1 Precharge→ time EE 42 fall 2004 lecture 38

  6. DRAM/SRAM tradeoffs • By it’s nature, DRAM isn’t built for speed • Response time dependent on capacitive circuit properties which get worse as density increases • DRAM process isn’t easy to integrate into CMOS process • DRAM is off chip • Connectors, wires, etc introduce slowness • IRAM efforts looking to integrating the two • Memory Architectures are designed to minimize impact of DRAM latency • Use dram for high density, store data which is used often in smaller, higher speed SRAM cache. EE 42 fall 2004 lecture 38

  7. Nonvolatile memory • One disadvantage of both SRAM and DRAM is that if power is removed, the contents is lost. • One solution is to use SRAM designed to use very little current, and then to maintain power with a battery • Another solution is to use a memory type which physically alters the cell, such as EE memory EE 42 fall 2004 lecture 38

  8. Trapped charge • Most current nonvolatile memories use a modified MOSFET with a floating gate • The floating gate can be charged or discharged by electrons moving through the oxide. • In the oldest technology, the EPROM, the floating gate is charged by hot electrons tunneling through a thin oxide, but can only be discharged by ultraviolet light exposure to the whole chip EE 42 fall 2004 lecture 38

  9. UV Erase PROM Control Gate Floating Gate SiO2 SiO2 + + n n Thin Oxide Drain Source p-Substrate

  10. UV EPROM UV Light Vgg Vss Vdd ------------------ +++++++++++ Hot electrons n+ n+ n+ n+ Program Erase

  11. Electrical EPROM Control Gate Storage Gate n+ n+

  12. EEProm • In an EEPROM, (electrically erasable) the electrons can be tunneled back off the floating gate by applying a high voltage between the control gate and the source EE 42 fall 2004 lecture 38

  13. Programming/erasing • The floating gate programmed by running a current of electrons from the source to the drain, then placing a large voltage on the control gate, a strong enough electric field to let them go through the oxide to the floating gate, a process called hot-electron injection. • To erase a flash cell, a large voltage differential is placed between the control gate and source, which pulls the electrons off the floating gate through Fowler-Nordheim tunneling, a quantum mechanical tunneling process. EE 42 fall 2004 lecture 38

  14. EEPROM Vss Vss Vdd Vdd ++++++++eee +++ eee - - - - - - - - - - Hot electrons n+ n+ n+ n+

  15. Flash • Flash memory can be erased and reprogrammed in units of memory called blocks. It is a form of EERAM, which, unlike flash memory, is erased and rewritten at the byte level. • Erasing and rewriting as a block means faster writing times for large blocks of data. • Flash memory gets its name because the microchip is organized so that a section of memory cells are erased in a single action or "flash." • The erasure is caused by Fowler-Nordheim tunneling in which electrons go through a thin oxide to remove an electronic charge from the floating gate. EE 42 fall 2004 lecture 38

  16. Memory Comparison grid

  17. Flash Memory Comparison • FLASH cells can be roughly made two or three times smaller than the EEPROM • Flash memory allows faster and more frequent programming than EPROM • Flash memory provides better data reliability than battery-backed SRAM • Flash memory fits in applications that might otherwise have used ROM (EEPROM), battery-backed RAM, or magnetic mass storage

  18. Advanced memory technologies • Ferroelectric Random Access Memory (FRAMs) • Magnetoresistive Random Access Memories (MRAMs) • Experimental Memories • Quantum-Mechanical Switch Memories • Single Electron Memory • Tunneling Magnetic Junction RAM (TMJ-RAM): • Speed of SRAM, density of DRAM, non-volatile (no refresh) • “Spintronics” electron spin effects transport • Same technology used in the read heads of high-density disk-drives: Giant magneto-resistive effect

  19. FRAM EE 42 fall 2004 lecture 38

  20. Ferroelectric material EE 42 fall 2004 lecture 38

  21. Tunneling Magnetic Junction EE 42 fall 2004 lecture 38

More Related