Cadence’s Signoff Summit Teething Signoff – You have to own it

1. Cadence’s Signoff SummitTeething Signoff – You have to own it Jim Hogan 11/21/2013

2. Why is technology important? Homo habilis Starting with fire – it is has always been about life expectancy and the quality of life through the use of tools

4. Source: CDC

7. Chip are going into people, the internet of things, not just some mainframe at an insurance company. Which means that the power envelope and voltage behavior - reliability - become critical Technology that will protect our troops, treat heart arrhythmias, monitor a sleeping baby’s temperature and maybe one day prevent brain seizures Biostamp Extend human capabilities by making high-performance electronics virtually invisible, conformal, and wearable

8. Electronics are rigid and boxy Most of the electronic systems that power our digital life are flat and inflexible. That works for our phones and computers, but not our bodies. THE REALITY: Humans are soft and curvy It’s not rocket science that skin and organs are delicate and far from two-dimensional

10. Chips are going into mobile chips, you are working on advanced nodes with super specs, which means you have to have ultra-precise timing.

11. Transistors are shrinking - but atoms aren’t! traditional 22nm sub 10 nm Source: A. Asenov, "Statistical Nano CMOS Variability and Its Impact on SRAM", Springer, 2010

12. Multimode distributions and models Source: Gold Standard Simulations Dopant location/concentration variation Variation in roughness of circuit features

13. Source: Gold Standard Simulations

14. FF/SS Corners no longer Applicable Example on GF 28-nm, PLL VCO, Avg. Duty Cycle Non-Gaussian distribution SS FF/SS don’t capture the bounds of the distribution! FF/SS were designed to bracket performance at device level, for (digital) speed and power outputs. Not well-suited to analog / RF circuits. FF

15. FF/SS Corners no longer Applicable

16. Rapid increase in Mixed-Signal content MGC, 2011

19. The tool names are the same but … DRC - Geometric verification, this involves verifying if the design can be reliably manufactured given current photolithography limitations. In advanced process nodes, DFM rules are upgraded from optional (for better yield) to required. LVS - Schematic verification, this is used to verify that the placement and routing of the standard cells in the design has not altered the functionality of the constructed circuit. Formal verification - Here, the logical functionality of the post-layout netlist (including any layout-driven optimization) is verified against the pre-layout, post-synthesis netlist. Voltage/IR drop analysis - Verifies if the power grid is strong enough to ensure that the voltage representing the binary high value never dips lower than a set margin (below which the circuit will not function correctly or reliably) due to the combined switching of millions of transistors. Power Binning Signal integrity analysis - Noise due to crosstalk and other issues is analyzed, and its effect on circuit functionality is checked to ensure that capacitive glitches are not large enough to cross the threshold voltage of gates along the data path. Static timing analysis (STA) – Increasingly being superseded by statistical static timing analysis (SSTA), STA is used to verify if all the logic data paths in the design can work at the intended clock frequency, especially under the effects of on-chip variation. STA is run as a replacement for SPICE, because SPICE simulation's runtime makes it infeasible for full-chip analysis modern designs. Electromigration/Reliability - To ensure a minimum lifetime of operation at the intended clock frequency without the circuit succumbing to Electromigration.

20. SoC teams and ownership for the sign-off flow Historically engineering managers try to change the flow as least as possible. Leave the tried and true in place, change out only the critical. That reduces the risks, and lets them isolate the new stuff. The devil you know versus the devil you don’t. Advance process is getting much higher variance - FEOL and BEOL, doubling the number of corners and variance adjustments - so you have to consider all of that. The process geometries are getting much smaller, so analog effects are getting bigger - you have to consider all of that too. Your frequency is increasing, power budget is shrinking, memory width is doubling, number of cores is rising, and more functionality keeps getting added. Which means your timing footprint grew, slack decreased, and timing runs increased - so you have to consider that. Systems are rushing to new processes at revision V0.5, this doesn’t allow the foundry the time to stabilize and characterize the new process. We are entering a phase where the sign-off methodology and the tool flow itself is a source of risk - not just signing off.  Rather than changing a few things, everything has to be re-evaluated

21. Thank you