1 / 13

GBT Specification Workgroup: 3 rd Meeting

GBT Specification Workgroup: 3 rd Meeting. Paulo Moreira 2009/05/05 - CERN. Outline. Link specification group Specification documents GBT project activities (2008 to date) ASIC FPGA Feedback from the experiments: ALICE ATLAS CMS LHCB NON-SLHC. Link specification group.

zona
Download Presentation

GBT Specification Workgroup: 3 rd Meeting

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. GBT Specification Workgroup: 3rd Meeting Paulo Moreira 2009/05/05 - CERN

  2. Outline • Link specification group • Specification documents • GBT project activities (2008 to date) • ASIC • FPGA • Feedback from the experiments: • ALICE • ATLAS • CMS • LHCB • NON-SLHC Paulo.Moreira@cern.ch

  3. Link specification group • Link specification group formed in 2008 • Members: • Electronics coordinators of: • ALICE, ATLAS, CMS and LHCb • Five members of the Radiation Hard Optical Link (RHOL) project • “Mandate”: • Identify the “GBT” needs of each experiment for the SLHC upgrade • Discuss the specification documents (before they are distributed within the collaborations). • Meetings: • 1st meeting (CERN – 2008/04/17) • ALICE, ATLAS, CMS and LHCb electronics coordinators presented outlooks of their requirements for SLHC. • 2nd meeting (CERN – 2008/11/14) • GBT system proposal was presented to the electronics coordinators. • 3rd meeting (CERN – 2009/05/05) • Link specification feedback Paulo.Moreira@cern.ch

  4. Specification documents • Share point web site created (2008): • http://cern.ch/proj-gbt • Specification documents: • GBTX specifications (V1.0, January 2009) • GBTIA specifications (V1.7, May 2008) • GBLD specifications (V2.0, July 2008) • GBT-SCA specifications (V1.5, June 2008) • E-Port IP 7B8B specifications (V0.1, December 2008) • E-Port IP Core specifications (V0.2, January 2009) • E-Port IP HDLC specs (V0.2, January 2009) Paulo.Moreira@cern.ch

  5. ASIC design activities • GBLD • Tape out: July 2008 • Silicon available: January 2009 • Tests still to be done! (Perugia group responsible for the tests hasn’t produced the PCB yet!) • GBTIA: • Tape out: July 2008 • Silicon available: January 2009 • Chip tested with excellent results • GBT-SERDES: • Design ongoing: • Serializer: 100% (-δ) • Clock-phase shifter: 100% (-δ) • CDR circuit: 30% • Digital logic: 80% • C4 package design launched (Endicott) . • E-Ports: • RTL code has been developed for the 7B/8B and HDLC favours of the E-Ports. • Scalable Low-Voltage Signaling (SLVS) links tested • Driver and receiver designed (test chip to be submitted in May 11) • GBT-SCA: • Specification work is undergoing Paulo.Moreira@cern.ch

  6. FPGA design activities • Compatibility of the GBT protocol with modern FPGAs proved. • XILINX Virtex-4FX • Successful Electrical & Optical loop-back @ 4.8Gb/s • ALTERA StratixII GX • Successful “optical” loop-back tests @ 4.8 Gb/s and @ 6.4 Gb/s Paulo.Moreira@cern.ch

  7. ALICE feedback • Only recently ALICE has shown interest on the GBT project: • For “TTC” applications • Very interested for DAQ (according to David Evans)… Paulo.Moreira@cern.ch

  8. ATLAS feedback • Questions: • What are the effects of SEUs on link synchronization? • Pixel: GBTX and optoelectronics components will be separated by a distance of 4 to 6 meters (radiation is too high for the optoelectronics). • Can that be done with addition of extra line drivers in and receivers? • Can the GBLD be used to drive cables and take advantage from the pre-emphasis functionality? • Comments: • Pixel: Mostly simplex links for data acquisition • Down-link bandwidth required is low • Some concerns about • Phase adjustment for the E-ports: automatic/programmable • DC balancing: • Sceptical about scrambling! • Recent interest in the 7B/8B solution • Favourite solution would be 8B/10B coding at the GBTX but that possibility has now be basically ruled out • Requests: • Make the E-Links configuration independent for output and input ports • Pixel: Space is at a premium: at least one of the linear dimensions of the package should be ≤ 1 cm • Pixel: In some cases would be desirable to run the GBTX at lower frequencies (e.g. 3.5 Gb/s) • About 10k GBTX will be needed Paulo.Moreira@cern.ch

  9. CMS feedback • Tracker: • ~10k GBTX needed • Bidirectional links needed • 10 Gb/s (at low power might be needed) • E-Links: • 2.5 m needed • (4 m might be necessary?) • An E-port architecture proposed (Alessandro Marchioro) • HCAL: • Parallel bus mode required Paulo.Moreira@cern.ch

  10. LHCB feedback - 1 • Most GBTX will be used in the simplex mode: • Only a few in duplex mode for clock and experiment control • FEC is considered a “big” overhead! • Not necessary for the up-links • Useful for the down-links (trigger and experiment control) • The use of 64B/66B is advocated • For some sub-detectors the GBTX will interface with COTS (mainly FPGAs) • Interfacing with “E-Links” might not be possible! • Support of industrial standard signalling is required • LVCMOS (1.5V) • 2.5 V and 3.3 V tolerant I/O • Some “specific” requests: • Idle and data frames • “Data valid” signal for bus modes • Built-in BER up to 1E-15 • 40, 80 and 160 MHz clocks • Up to 12 phase adjustable clocks • Include termination resistors on chip • Higher speed E-Links: • 2 × 800 Mb/s • 1 × 1.6 Gb/s • About 10k GBTX will be needed Paulo.Moreira@cern.ch

  11. LHCB feedback - 0 • GBT – SCA requests: • Is it possible to include a radiation monitor detector? • I2C interface: • Split the SDA signal in two SDA_IN and SDA_OUT • For easier buffering over “long” distances • Support: • PT1000s and PT100s Paulo.Moreira@cern.ch

  12. NON-SLHC feedback - PANDA • Very negative 1st feedback: • More recently (according to Gianni Mazza): • “… the GBT project raised a lot of interest in the GSI PANDA community…” • Main technical requirement: • Reference clock: 41.67 MHz (5 Gb/s) Paulo.Moreira@cern.ch

  13. Project Schedule 2008 Design and prototyping of performance critical building blocks: GBTIA, GBLD, Serializer, De-Serializer, Phase Shifter First tests of optoelectronics components SEU tests on PIN receivers Proceed with the link specification meetings General link specification 2009 Design/prototype/test of basic serializer/de-serializer chip GBT-SERDES Design/prototype/test of optoelectronics packaging GBTIA + PIN on TO CAN Detailed link specification document 2010 Prototype of “complete” GBTX chip Full prototype of optoelectronics packaging 2011 Extensive test and qualification of full link prototypes System demonstrator(s) with use of full link Schedule of the final production version is strongly dependent on the evolution of the LHC upgrade schedule Paulo.Moreira@cern.ch

More Related