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Monolithic SOI Detector Integration for High-Quality Sensor Systems

Discover the development and functionality of a fully depleted P+-N junction matrix integrated with CMOS electronics on a wafer-bonded SOI substrate. This innovative technology offers improved sensor sensitivity and high signal-to-noise ratio, paving the way for advanced sensor applications.

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Monolithic SOI Detector Integration for High-Quality Sensor Systems

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  1. Snowmass 2005 SOI detector R&D Antonio Bulgheroni on behalf of the SOI workgroup Massimo Caccia, Antonio Bulgheroni Univ. dell’Insubria / INFN Milano (Italy) M. Jastrzab, M. Koziel, W. Kucewicz, H. Niemiec*, M. Sapor AGH – University of Science and Technology – Krakow – Poland P. Grabiec, K. Kucharski, J. Marczewski, D. Tomaszewski Institute of Electron Technology – Warsaw – Poland *Scholarship holder of the Foundation for Polish Science

  2. Principle of SOI Monolithic detector Integration of a fully depleted p+-n junction matrix and the readout electronics in a wafer bonded SOI substrate Detector  Handle wafer High resistive (> 4 kcm, FZ) 400 µm thick conventional p+-n matrix Electronics  Device layer Low resistive (9-13 cm, CZ) 1.5 µm thick Standard CMOS technology

  3. PROS Monolithic: no need of any hydridization and consequent thickness reduction Fully depleted: high SNR, high sensitivity Standard CMOS electronics: both type of transistors Custom technology: will never become obsolete SOI pros and contra CONTRA • Non standard technology: requires dedicated process in non standard foundries • Thermal budget: high temperature processes for the electronics parts clash against the low thermal budget required for high quality p+-n junctions. • Low availability of SOI substrate: with detector grade handle wafer

  4. SOI development 2005 2002 2003 2004 Phase 1: Technology definition Phase 2: Small area prototype Phase 3: Full area fully functional sensor Developed by the SUCIMA collaboration within a EC project for medical applications. US Patent Application no. PCT/IT2002/000700 • Electronics design by the AGH team • Technological implementation at IET on a 3µm production line

  5. Phase 1: technology definition Two steps procedure: • Definition of the technology filetest structure • Readout electronics functionality AMS 0.6 multi-project run

  6. SOI test structures / 1 Structure for electronics circuit characterization Detector prototypes (8x8 pixels) w/ and w/o charge injection pad. Structure for technological parameter extraction

  7. SOI test structures / 2 Transfer and output characteristics of NMOS with W/L=20/10 and 40/20 gds  428 nS @ VGS=2.3 V for W/L = 20/10 gds  196 nS @ VGS=2.3 V for W/L = 40/20

  8. Electronics functionality assessment / 1 Readout electronics part in AMS 0.6 • 2 fully functional matrices 16x16 pixels with different pixel addressing circuitries • 1 smaller 5x5 matrix with only the analog part

  9. Electronics functionality assessment / 2 • Measured noise ~ 1.78 mV • 20 mV signal injected every fourth pixel • Test of the CDS processing with 5 threshold.

  10. Phase 2: small area prototype / 1 • Basic 3 trans. architecture only slightly modified with PMOS • Single cell dimensions are 140 x 122 m2. • Matrix dimensions: 1120 m x 976 m • Not surrounded by guardring

  11. Phase 2: small area prototype / 2 • Charged particle sensitivity with radioactive sources • Linearity and dynamic range with infrared laser 90Sr Linearity

  12. Functionally independent quarter of the detector No dead area, preserved pitch Phase 3: full area sensor design

  13. 128 x 128 pixels on 2.4 x 2.4 cm2 sensitive area Dimensions: 150x150m2 Input capacitance similar to test structures  similar signals levels Larger PMOS in transmission gate  improved linearity Detector cavity Input protection Input MOSFET Guard Sensor characteristics

  14. Preliminary results • Sensor sensitivity observed with laser pointer and α particles. • Dynamic range up to 100 MIP • Charge to voltage gain 3.6 mV/fC • Problems with production yield: only ¾ of the best chip fully functional • Readout frequency up to 4 MHz

  15. Future plans / 1 • Proof of principle accomplished taking advantage of IET. Full cost 650 k€ (of which for personnel 200 k€) Partner foundry with a primitive 3µm production line Looking for another partner (device company) with a more advanced technology Contacts positively established with Hamamatsu 1 year ago

  16. Future plans / 2 • Next formal meeting with Hamamatsu during Pixel 2005 conference in September with the definition of a development plan • Interests from many groups: INFN, AGH, KEK, BONN

  17. Silicon on Insulator technology • CMOS electronics • High resistivity fully depleted sensitive volume • Not standard process • Development started off 3 years ago • Proof of principle accomplished • ILC dedicated development being defined with a partner company 90Sr INSUBRIA + INFN (ITALY), IET + AGH (POLAND)

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