EE466/586 VLSI Design

1. EE466/586VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu

2. Lecture 28 ROM

3. Read-Only Memory Cells BL BL BL VDD WL WL WL 1 BL BL BL WL WL WL 0 GND Diode ROM MOS ROM 1 MOS ROM 2

4. Diode ROM • Does not isolate the bit line from the word line. • All current required to charge the bit line capacitance has to be provided by the word line and its drivers • Better approach is to use an active device in the cell • All output-driving current is provided by the transistor

5. MOS OR ROM BL [0] BL [1] BL [2] BL [3] WL [0] V DD WL [1] WL [2] V DD WL [3] V bias Pull-down loads

6. MOS NOR ROM V DD Pull-up devices WL [0] GND WL [1] WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3]

7. Principle of Operations • Bits arestored according to the presence or absence of a transistor switch at each row-column intersection. • A column goes low when any row, joined to the column with a transistor, is raised to a high level. • In normal operation, all but one row line is held low. • When a selected wordline is raised to VDD , all transistors present is that row are turned on. • The columns to which they are connected are pulled low. • The remaining columns with transistors missing in their respective rows are held high by the pull-up or the load devices.

8. MOS NOR ROM • Pseudo-NMOS NOR gate with the word lines as inputs. • Under the normal operating conditions, only one of the word line goes high, and, at most, one of the pull down devices is turned on. • To keep the cell size and bit line capacitance small, the pull-down device should be kept as close as possible to minimum size. • Resistance of the pull-up device must be larger than that of the pull-down to ensure an adequate low level. • Affects low-to-high transition

9. Sizing • Difference between memory and logic design • In the NOR ROM, we can trade off noise margin for performance by letting the VOLof the bit line to be at a higher value. • The pull-up device can be widened to improve the low-to-high transition.

10. MOS NAND ROM V DD Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] All word lines high by default with exception of selected row

11. MOS NAND ROM • All transistors of the pull-down chain must be on to produce a low value. • All word lines are high by default with the exception of the selected row, which is set to 0. • Transistors on non selected rows are turned on • If no transistor is present on the intersection between the row and column of interest, then since all other transistors on the series chain are selected, the output is pulled low, and the stored value is 0. • When a transistor present at the intersection is turned off then the associated word line is brought low. • Results in a high output

12. Precharged MOS NOR ROM V f DD pre Precharge devices WL [0] GND WL [1] WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.

13. D G S Non-Volatile MemoriesThe Floating-gate transistor (FAMOS) Floating gate Gate Source Drain t ox t ox + +_ n n p Substrate Schematic symbol Device cross-section

14. FAMOS • Extra polysilicon strip between the gate and the channel. • This strip is not connected to anything • Applying a high voltage between the source and gate terminals creates a high electric field • Avalanche injection • Electrons acquire sufficient energy and traverse through the first oxide insulator, so that they get trapped on the floating gate • The trapping of electrons on the floating gate effectively drops voltage on the gate.

15. FAMOS (Cont’d) • The negative charge accumulated on the floating gate reduces the electric field over the oxide so that ultimately it becomes incapable of accelerating any more electrons. • Removing the voltage leaves the induced negative charge in place, which results in a negative voltage on the intermediate gate. • Effective increase in threshold voltage.

16. 20 V 0 V 5 V 20 V 0 V 5 V 10 V 5 V 5 V 2.5 V 2 2 S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V . T Floating-Gate Transistor Programming

17. A “Programmable-Threshold” Transistor The charge injected onto the floating gate effectively shifts the I-V curves of the transistor.

18. FLOTOX EEPROM Gate Floating gate I Drain Source V 20 – 30 nm -10 V GD 10 V 1 1 n n Substrate p 10 nm Fowler-Nordheim I-V characteristic FLOTOX transistor

19. FLOTOX EEPROM (Cont’d) • FLOTOX (floating gate tunneling oxide) transistor injects or removes charges from a floating gate through tunneling. • Dielectric separating the floating gate from the channel and drain is reduced in thickness to about 10 nm or less • When a voltage of approx. 10 v is applied over the thin insulator, electrons travel to and from the floating gate through the Fowler-Nordheim tunneling. • Injectingelectrons onto the floating gate raises the threshold, while the reverse operation reduces VT

20. V DD EEPROM Cell BL WL Absolute threshold control is hard Unprogrammed transistor might be depletion  2 transistor cell

21. Flash • Combination of EPROM and EEPROM. • Most Flash EEPROM devices use the avalanche hot-electron injection to program the device and use Fowler-Nordheim tunneling for erase. • Erasure is performed in bulk. • Extra access transistor is not needed.

22. Basic Operations in a NOR Flash Memory―Erase

23. Erase Operation • A 0 v gate voltage is applied, combined with a high voltage at the source • Electrons, if any, at the floating gate are ejected to the source by tunneling • All cells are erased simultaneously. • The different initial values of the cell threshold voltages, as well as variations in the oxide thickness, may cause variations in the threshold voltage at the end of the erase operation

24. Erase Operation • Before applying the erase pulse, all the cells in the array are programmed so that all the thresholds start approx. at the same value. • After that, an erase pulse of controlled width is applied. Subsequently the whole array is read to check whether or not the cells have been erased.

25. Basic Operations in a NOR Flash Memory―Write

26. Write • A high voltage pulse is applied to the gate of the selected device. • If a “1” is applied to the drain at that time, hot electrons are generated and injected onto the floating gate, raising the threshold • If not, the floating gate remains in the previous state of no electrons, corresponding to a “0” state.

27. Basic Operations in a NOR Flash Memory―Read