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NIOS II Ethernet Communication Final Presentation

NIOS II Ethernet Communication Final Presentation. By: Gilad Shterenshis Supervisor: Ina Rivkin Winter 2008. Content. Background and Project Goals Development Tools NIOS II System Design Flow SOPC System Design Steps Interface Project Milestones. Background and Project Goals.

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NIOS II Ethernet Communication Final Presentation

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  1. NIOS II Ethernet CommunicationFinal Presentation By: Gilad Shterenshis Supervisor: Ina Rivkin Winter 2008

  2. Content • Background and Project Goals • Development Tools • NIOS II System Design Flow • SOPC System • Design Steps • Interface • Project Milestones

  3. Background and Project Goals • Previous project: Implementation of simple calculator with Altera DE2 Board (Cyclone II) • Experiencing development tools and design flow • VHDL • Schematic editor • Current project: Create simple calculator in NIOS II processor using Ethernet interface • Implement Ethernet interface to the NIOS II w/o OS • Create HW environment for NIOS II processor • Create small calculator program in C/C++

  4. Development Tools • Software: • Quartus II 8.1 • SOPC Builder 8.1 • NIOS II IDE 8.1 • Aux S/W • Ethereal - Ethernet Sniffer • Colasoft Packet Builder • Hardware: • Altera DE2 Board • Cyclone II FPGA • Fast Ethernet Controller • PC

  5. DM9000A ETH Controller • Fast Ethernet MAC controller • General processor I/F • 10/100 PHY • AUTO-MDIX

  6. NIOS II System Design Flow SOPC Builder: Define & Generate System Quartus II: HW Development NIOS II IDE: SW Development Integration Sim/HW

  7. Project Steps • Build a simple SOPC system • Using On-Chip memory only • Small C library (no user input) • Calculator with RS-232 UART I/F • Using SDRAM memory • Running DE2_NET Example • Loop back cable • Display sent packets • Coding calculator S/W • Generating Ethernet packets • Integration and Debug

  8. UART System • Using RS-232 serial interface (or JTAG UART) • Simple S/W calculator • SDRAM usage

  9. SOPC Major Components LCD JTAG UART UART NIOS II core PIO Ethernet core SDRAM Memory TRI-STATE BRIDGE On-Chip Memory FLASH Memory

  10. SOPC Builder

  11. NIOS II Processor Core

  12. System Setup

  13. Packet Sending and Receiving • The controller add and remove 4 bytes of checksum • The controller filters packets by MAC address • If a packet is received, the NIOS gets an interrupt • The NIOS read the packet from the controller

  14. S/W Operation Sequence • Main • Initiate Controller and peripherals • Register function for interrupt • Main loop - Transmit UDP packets with result embedded • If packet received – Initiate controller • Function: ethernet_interrupts • Receiving packet • Check IP (screen multicast messages) • Read packet data • Build numbers • Calculate result (print to terminal)

  15. Using UDP • Simple, one packet communicating • Point to point • No ACK/NAK required

  16. NIOS II Terminal • Sending packets: • Receiving packets:

  17. Ethernet Sniffer • PC Packet:

  18. Ethernet Sniffer • NIOS II packet:

  19. Ethernet Packet Builder • UDP packets • Enable entering math exercise

  20. Improvements • GUI / Web browser I/F • Fields for entering arguments and operation • Result Field • Screen non related messages

  21. Project Milestones • Characterization presentation - 7/01/09 • Tutorials • Tools learning • Implementing simple system • NIOS II • SW - calculator • UART RS232 • LCD • Implementing ETH I/F • H/W development • S/W coding • Integration • Final presentation • Project summary submission

  22. Thank You!

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