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MIPS Pipeline Implementation: Five-Stage Data Path and Execution Cycle

This lecture covers the implementation of pipelining in the MIPS architecture, including the five-stage data path and the execution cycle. It discusses how MIPS instructions work and how they are pipelined. The lecture also includes examples and explanations of the different stages in the execution cycle.

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MIPS Pipeline Implementation: Five-Stage Data Path and Execution Cycle

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  1. Lecture 06: PipeliningImplementation Kai Bu kaibu@zju.edu.cn http://list.zju.edu.cn/kaibu/comparch2016

  2. Assignment 1 due Lab 1 Report due Lab 2 Demo due April 20 Report due April 27

  3. MIPS Five-Stage Data PathUnderneath Pipelining IF ID EX MEM WB

  4. Data PathUnderneath Pipelining lab & exam

  5. Data PathUnderneath Pipelining IF ID EX MEM WB

  6. Preview under MIPS architecture • How an MIPS instruction works? • How MIPS instructions pipleline?

  7. Appendix C.3-C.4

  8. How an unpipelined MIPS instruction works?

  9. MIPS Instruction • at most 5 clock cycles per instruction • IF ID EX MEM WB

  10. IF IF ID EX MEM WB • Instruction Fetch cycle IR ← Mem[PC]; NPC ← PC + 4; IR: instruction register NPC: next sequential PC

  11. ID IF ID EX MEM WB • Instruction Decode/register fetch A ← Regs[rs]; B ← Regs[rt]; Imm ← sign-extended immediate field of IR (lower 16 bits)

  12. EX IFID EX MEM WB • Execution/effective address cycle ALU operates on the operands from ID: 4 functions depending on the instr type -Memory reference -Register-register ALU instruction -Register-immediate ALU instruction -Branch

  13. EX IFID EX MEM WB • Execution/effective address cycle -Memory reference ALUOutput ← A + Imm; ALU adds the operands to form effective address

  14. EX IFID EX MEM WB • Execution/effective address cycle -Register-register ALU instr ALUOutput ← A func B; ALU performs the operation specified by function code on the values in register A & register B

  15. EX IFID EX MEM WB • Execution/effective address cycle -Register-Immediate ALU Instr ALUOutput ← A op Imm; ALU performs the operation specified by opcode on the values in register A & reg IMM

  16. EX IFID EX MEM WB • Execution/effective address cycle -Branch ALUOutput ← NPC + (Imm<<2); Cond ← (A == 0); ALUOutput -> branch target BEQZ: comparison against 0

  17. EX IFID EX MEM WB • Execution/effective address cycle -Branch ALUOutput ← NPC + (Imm<<2); Cond ← (A == 0); ALUOutput -> branch target BEQZ: comparison against 0 Why <<2? http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Mips/addr.html

  18. MEM IFID EX MEM WB • MEMory access/branch completion update PC for all instr: PC ← NPC; -Memory Access LMD ← Mem[ALUOutput]; load Mem[ALUOutput] ← B; store -Branch if (cond) PC ← ALUOutput; Load Memory Data register

  19. WB IFID EX MEMWB • Write-Back cycle -Register-register ALU instruction Regs[rd] ← ALUOutput; -Register-immediate ALU instruction Regs[rt] ← ALUOutput; -Load instruction Regs[rt] ← LMD;

  20. Put It All Together

  21. MIPS Instruction IF ID EX MEM WB IR ← Mem[PC]; NPC ← PC + 4;

  22. MIPS Instruction IF ID EX MEM WB A ← Regs[rs]; B ← Regs[rt]; Imm ← sign-extended immediate field of IR (lower 16 bits)

  23. MIPS Instruction IF ID EX MEM WB ALUOutput ← A + Imm; ALUOutput ← A func B; ALUOutput ← A op Imm; ALUOutput ← NPC + (Imm<<2); Cond ← (A == 0);

  24. MIPS Instruction IF ID EX MEM WB LMD ← Mem[ALUOutput]; Mem[ALUOutput] ← B; if (cond) PC ← ALUOutput;

  25. MIPS Instruction IF ID EX MEM WB Regs[rd] ← ALUOutput; Regs[rt] ← ALUOutput; Regs[rt] ← LMD;

  26. MIPS Instruction Demo • Prof. Gurpur Prabhu, Iowa State Univ http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/DLXimplem.html • Load, Store • Register-register ALU • Register-immediate ALU • Branch

  27. Load

  28. Load: IF Load

  29. Load: ID Load

  30. Load: EX Load

  31. Load: MEM Load

  32. Load: WB Load

  33. Store

  34. Store: IF Store

  35. Store: ID Store

  36. Store: EX Store

  37. Store: MEM Store

  38. Store: WB Store

  39. IF Register-Register ALU: MEM

  40. IF Register-Register ALU: MEM

  41. ID Register-Register ALU: MEM

  42. EX Register-Register ALU: MEM

  43. MEM Register-Register ALU: MEM

  44. WB Register-Register ALU: MEM

  45. IFEM Register-Imm ALU:MEM

  46. IFEM Register-Imm ALU: MEM

  47. IDEM Register-Imm ALU: MEM

  48. EXEM Register-Imm ALU: MEM

  49. MEMEM Register-Imm ALU: MEM

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