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Synchronous Counter Design using Xilinx and Logic Gates

Design a synchronous counter with one input (X) and a 3-bit state (Z) using a counter designed in Xilinx and additional logic gates. Complete the hardware design, draw the logic circuit diagram, synthesize and simulate the circuits, and implement them using the FPGA demo-board.

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Synchronous Counter Design using Xilinx and Logic Gates

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  1. Lab 5: Counter Applications • Outline • Design a special-type synchronous sequential circuit using a counter • Schematic entry

  2. JA QA JA QB JA QC KA KA KA • Synchronous Binary Counter • A 3-stage synchronous binary counter MSB LSB Output CK QC QB QA Output MSB 1 Output LSB 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 CK 7 1 1 1

  3. A more general case • has a main loop S0 X=0,1 X=0,1 000 S6 S1 110 001 X=0 X=0,1 X=1 X=0 X=0 S5 101 S2 010 X=1 X=1 100 011 X=1 S4 S3 X=0

  4. Design procedure: • a. Use a “straight binary state assignment” for the states in the main loop. • b. Use the “clear” input when transitions to state 0 are required. • c. Activate the “counting function” when transitions between successive states in the main loop are required. • d. Use the “load” input when transitions out of the normal counting sequence (except transitions to state 0) are required.

  5. Derivation of Counter Inputs X C B A C+B+A+ CLEAR LOAD DCDBDA PT 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 1 1 0 0 0 x x x 1 1 x x x 1 1 1 x x x 1 0 x x x x x 1 0 1 1 0 x 1 1 x x x 0 1 0 0 1 1 x 0 x x x x x x x x x x x 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 0 0 0 x x x 1 1 x x x 1 1 1 x x x 1 1 1 x x x 1 1 1 x x x 1 1 1 x x x 1 1 1 x x x 1 0 x x x x x x x x x x x

  6. Karnaugh maps XC XC XC 00 01 11 10 00 1 1 1 1 01 1 1 1 1 11 1 x x 1 10 0 0 0 1 00 01 11 10 00 1 1 1 1 01 1 0 1 1 11 0 x x 1 10 x x x 1 00 01 11 10 00 1 0 1 1 01 1 x 1 1 11 x x x 1 10 x x x 1 BA BA BA Clear =A+B’+XC’ Load =A+X+B’C’ PT = X+C’ XC XC XC 00 01 11 10 00 x x x x 01 x 0 x x 11 1 x x x 10 x x x x 00 01 11 10 00 x x x x 01 x 1 x x 11 1 x x x 10 x x x x 00 01 11 10 00 x x x x 01 x 1 x x 11 0 x x x 10 x x x x BA BA BA DC = B DB = 1 DA = C

  7. Realization D CBA C X’ P T C X’ 74S163 + Clear A’ B DD DC DB DA Load X’ A B C B 1 CLOCK +

  8. 1 1 000 0 0 101 001 1 0 0 1 100 010 0 0 1 1 011 Lab Assignment • Design a synchronous counter • one input x and one 3-bits state z • using a counter designed in Xilinx and extra logic gates • the state diagram

  9. (i) Complete the hardware design of this synchronous sequential circuit using a counter, and logic gates. (ii) Draw the logic circuit diagram using schematic editor (iii) Synthesize and simulate the circuits (iv) Implement the circuits using the FPGA demo-board

  10. Parts • The Parts required in this experiment are listed below: • cd4rle: synchronous 4-bit binary counter with synchronous clear and load (designed in Xilinx) • Cpt_di: a combinational circuit • Clk1Hz: a clock with 1 Hz frequency. • Seven_segment：a module control the seven_segment displayer input requirement： • A countdown and countup counter, depend on the input • When clock is arrive, add or subtract counter value • The top module must implemented in schematic design, cannot use verilog code

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