1 / 80

Processor

Processor-memory bus. Memory. Processor. Bus Adapter. I/O Device. I/O Device. Expansion bus. I/O Device. I/O Bus. Bus Adapter. I/O Device. I/O Device. The Operating System ( OS) controls I/O processes.

dicke
Download Presentation

Processor

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Processor-memory bus Memory Processor Bus Adapter I/O Device I/O Device Expansion bus I/O Device I/O Bus Bus Adapter I/O Device I/O Device

  2. The Operating System ( OS) controls I/O processes

  3. The Operating System ( OS) controls I/O processes • OS contains the low level programs that control the • I/O device. ( Device Drivers, usually provided by • the device manufacturer)

  4. The Operating System ( OS) controls I/O processes • OS contains the low level programs that control the • I/O device. ( Device Drivers, usually provided by • the device manufacturer) • Limits access to Users for Protection and Resource • Scheduling. ( Some programs violate this)

  5. The Operating System ( OS) controls I/O processes • Contains the low level programs that control the • I/O device. ( Device Drivers, usually provided by • the device manufacturer) • Limits access to Users for Protection and Resource • Scheduling. ( Some programs violate this) • OS must give commands to devices and reads • status from Devices

  6. The Operating System ( OS) controls I/O processes • Contains the low level programs that control the • I/O device. ( Device Drivers, usually provided by • the device manufacturer) • Limits access to Users for Protection and Resource • Scheduling. ( Some programs violate this) • OS must give commands to devices and read • status from Devices • 4. Devices must notify the OS of changes

  7. The Operating System ( OS) controls I/O processes • Contains the low level programs that control the • I/O device. ( Device Drivers, usually provided by • the device manufacturer) • Limits access to Users for Protection and Resource • Scheduling. ( Some programs violate this) • OS must give commands to devices and read • status from Devices • 4. Devices must notify the OS of changes • 5. Data must be transferred between memory and • an I/O device

  8. OS must give commands to devices and read • status from Devices • Special I/O instructions • Store Register xx in Device Address yy

  9. OS must give commands to devices and read • status from Devices • Special I/O instructions • Store Register xx in Device Address yy • Device address is put on I/O control lines and • the data is put on the I/O data lines

  10. OS must give commands to devices and read • status from Devices • Special I/O instructions • Store Register xx in Device Address yy • Device address is put on I/O control lines and • the data is put on the I/O data lines • Write from Device Address yy to a Register • or Memory location

  11. OS must give commands to devices and read • status from Devices • Special I/O instructions • Store Register xx in Device Address yy • Device address is put on I/O control lines and • the data is put on the I/O data lines • Write from Device Address yy to a Register • or Memory location • Constraining for unknown devices

  12. OS must give commands to devices and read • status from Devices • Special I/O instructions • Memory Mapped I/O • Memory Address Space is assigned to Devices.

  13. OS must give commands to devices and read • status from Devices • Special I/O instructions • Memory Mapped I/O • Memory Address Space is assigned to Devices. • A Write to that address goes to a device controller • register and not to the memory ( Commands)

  14. OS must give commands to devices and read • status from Devices • Special I/O instructions • Memory Mapped I/O • Memory Address Space is assigned to Devices. • A Write to that address goes to a device controller • register and not to the memory ( Commands) • A Read of that address comes from a device • controller register and not the memory ( Status)

  15. OS must give commands to devices and read • status from Devices • Special I/O instructions • Memory Mapped I/O • Memory Address Space is assigned to Devices. • A Write to that address goes to a device controller • register and not to the memory ( Commands) • A Read of that address comes from a device • controller register and not the memory ( Status) • Memory Map defined by software for the installed • I/O controllers ( Flexibility and Expandability)

  16. Devices must notify the OS of changes • Polling • Processor periodically reads the status of the I/O • Ex: key depressed, print complete, buffer full

  17. Devices must notify the OS of changes • Polling • Processor periodically reads the status of the I/O • Ex: key depressed, print complete, buffer full • Processor is in complete control

  18. Devices must notify the OS of changes • Polling • Processor periodically reads the status of the I/O • Ex: key depressed, print complete, buffer full • Processor is in complete control • Polling loop in OS is overhead

  19. Devices must notify the OS of changes • Polling • Processor periodically reads the status of the I/O • Ex: key depressed, print complete, buffer full • Processor is in complete control • Polling loop in OS is overhead • Effective on slow devices that initiate I/O • Ex: keyboard and Mouse

  20. Devices must notify the OS of changes • Polling • Processor periodically reads the status of the I/O • Ex: key depressed, print complete, buffer full • Processor is in complete control • Polling loop in OS is overhead • Effective on slow devices that initiate I/O • Ex: keyboard and Mouse

  21. Devices must notify the OS of changes • Polling • Processor periodically reads the status of the I/O • Ex: key depressed, print complete, buffer full • Processor is in complete control • Polling loop in OS is overhead • Effective on slow devices that initiate I/O • Ex: keyboard and Mouse • Not efficient for fast devices

  22. Devices must notify the OS of changes • Polling • Interrupt-driven • Device controller asserts interrupt signal line and • loads interrupt status register.

  23. Devices must notify the OS of changes • Polling • Interrupt-driven • Device controller asserts interrupt signal line and • loads interrupt status register. • Processor checks for interrupt at the start of • each new instruction ( in parallel)

  24. Devices must notify the OS of changes • Polling • Interrupt-driven • Device controller asserts interrupt signal line and • loads interrupt status register. • Processor checks for interrupt at the start of • each new instruction ( in parallel) • Processor recognizes interrupts on a priority basis

  25. Devices must notify the OS of changes • Polling • Interrupt-driven • Device controller asserts interrupt signal line and • loads interrupt status register. • Processor checks for interrupt at the start of • each new instruction ( in parallel) • Processor recognizes interrupts on a priority basis • OS services the interrupt based on the Cause • register or vectored interrupt

  26. Devices must notify the OS of changes • Polling • Interrupt-driven • Device controller asserts interrupt signal line and • loads interrupt status register. • Processor checks for interrupt at the start of • each new instruction ( in parallel) • Processor recognizes interrupts on a priority basis • OS services the interrupt based on the Cause • register or vectored interrupt • Enables a device to signal that data is ready to be • transferred or an operation has been completed

  27. The Operating System ( OS) controls I/O processes • Contains the low level programs that control the • I/O device. ( Device Drivers, usually provided by • the device manufacturer) • Limits access to Users for Protection and Resource • Scheduling. ( Some programs violate this) • OS must give commands to devices and read • status from Devices • 4. Devices must notify the OS of changes • 5. Data must be transferred between memory and • an I/O device

  28. Data must be transferred between memory and an I/O device • Processor Control • Data and Status transferred by Special Instruction • or Memory Mapped I/O

  29. Data must be transferred between memory and an I/O device • Processor Control • Data and Status transferred by Special Instruction • or Memory Mapped I/O • Polling or Interrupts are used

  30. Data must be transferred between memory and an I/O device • Processor Control • Data and Status transferred by Special Instruction • or Memory Mapped I/O • Polling or Interrupts are used • Fast device with blocks of data can excessively • load processor • Ex: hard disk and display

  31. Data must be transferred between memory and an I/O device • Processor Control • Direct Memory Access ( DMA) • I/O controller transfers block of data between device • and memory independent of the processor

  32. Data must be transferred between memory and an I/O device • Processor Control • Direct Memory Access ( DMA) • I/O controller transfers block of data between device • and memory independent of the processor • DMA transfer process • Processor initiates the device operation ( memory • address, number of bytes, enable bus master)

  33. Data must be transferred between memory and an I/O device • Processor Control • Direct Memory Access ( DMA) • I/O controller transfers block of data between device • and memory independent of the processor • DMA transfer process • Processor initiates the device operation ( memory • address, number of bytes, enable bus master) • DMA controller directly transfers block of data • between memory and device, under arbitration

  34. Data must be transferred between memory and an I/O device • Processor Control • Direct Memory Access ( DMA) • I/O controller transfers block of data between device • and memory independent of the processor • DMA transfer process • Processor initiates the device operation ( memory • address, number of bytes, enable bus master) • DMA controller directly transfers block of data • between memory and device, under arbitration • DMA sends interrupt to notify completion or error

  35. Data must be transferred between memory and an I/O device • Processor Control • Direct Memory Access ( DMA) • I/O controller transfers block of data between device • and memory independent of the processor • DMA transfer process • Processor initiates the device operation ( memory • address, number of bytes, enable bus master) • DMA controller directly transfers block of data • between memory and device, under arbitration • DMA sends interrupt to notify completion or error • Enables the processor to continue to operate during • data transfer

  36. I/O bus Control CPU/ Memory Data I/O 1 I/O 2 I/O 3 A bus master controls access to the bus

  37. I/O bus Control CPU/ Memory Data I/O 1 I/O 2 I/O 3 • A bus master controls access to the bus • Slaves request bus access

  38. I/O bus Control CPU/ Memory Data I/O 1 I/O 2 I/O 3 • A bus master controls access to the bus • Slaves request bus access • The bus master generates controls to make the • transfer

  39. I/O bus Control CPU/ Memory Data I/O 1 I/O 2 I/O 3 • A bus master controls access to the bus • Slaves request bus access • The bus master generates controls to make the • transfer • The processor is always a bus master and memory • is always a slave

  40. Typically want multiple bus masters, so need to decide which bus master gets control.

  41. Typically want multiple bus masters, so need to decide • which bus master gets control. • Bus Arbitration • Arbitration schemes are used to grant the bus based on: • Priority • Avoid lockout ( fairness)

  42. I/O and Caches • Polling or Interrupt- driven I/O under processor • control goes through cache ( virtual and performance)

  43. I/O and Caches • Polling or Interrupt- driven I/O under processor • control goes through cache ( virtual and performance) • DMA goes direct to main memory • Cache coherency problem • ( Cache and memory different) • Cache flushing with hardware support

  44. I/O and Caches • Polling or Interrupt- driven I/O under processor • control goes through cache ( virtual and performance) • DMA goes direct to main memory • Cache coherency problem • ( Cache and memory different) • Cache flushing with hardware support • Page boundaries in virtual memory • Stay within page boundaries or use virtual • addresses

  45. MOUSE Y Counter The movement of the Mouse increments or decrements the X and Y counters X counter

  46. MOUSE Y Counter The movement of the Mouse increments or decrements the X and Y counters. If the location of the cursor is updated 20 times per second it appears smooth to a human. X counter

  47. MOUSE Y Counter The movement of the Mouse increments or decrements the X and Y counters. If the location of the cursor is updated 20 times per second it appears smooth to a human. X counter GIVEN: • Poll at 40 times per second. • 2. Polling I/O routine takes 800 clock cycles • Each counter is 2 Bytes, Sample is 1 Word • Clock Rate is 500 MHz

  48. MOUSE GIVEN: • Poll at 40 times per second. • 2. Polling I/O routine takes 800 clock cycles • Each counter is 2 Bytes, Sample is 1 Word • Clock Rate is 500 MHz % Processor Usage? Each Polling Cycle is 1/40 sec Number of clock cycles each polling cycle = 500x106 clock cycles/sec * 1/40 sec = 12.5 x 106

  49. MOUSE GIVEN: • Poll at 40 times per second. • 2. Polling I/O routine takes 800 clock cycles • Each counter is 2 Bytes, Sample is 1 Word • Clock Rate is 500 MHz % Processor Usage? Each Polling Cycle is 1/40 sec Number of clock cycles each polling cycle = 500x106 clock cycles/sec * 1/40 sec = 12.5 x 106 % Processor Usage = 800 = 64 x 10-6 = 0.0064 % 12.5 x 106

More Related