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Single Cycle datapath

Single Cycle datapath. How to Design a Processor: step-by-step. 1. Analyze instruction set => datapath requirements the meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers possibly more

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Single Cycle datapath

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  1. Single Cycle datapath

  2. How to Design a Processor: step-by-step • 1. Analyze instruction set => datapath requirements • the meaning of each instruction is given by the register transfers • datapath must include storage element for ISA registers • possibly more • datapath must support each register transfer • 2. Select set of datapath components and establish clocking methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic

  3. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 immediate op rs rt 6 bits 5 bits 5 bits 16 bits 31 26 0 op target address 6 bits 26 bits The MIPS Instruction Formats • All MIPS instructions are 32 bits long. The three instruction formats: • R-type • I-type • J-type • The different fields are: • op: operation of the instruction • rs, rt, rd: the source and destination register specifiers • shamt: shift amount • funct: selects the variant of the operation in the “op” field • address / immediate: address offset or immediate value • target address: target address of the jump instruction

  4. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Step 1a: The MIPS-lite Subset for today • ADD and SUB • addU rd, rs, rt • subU rd, rs, rt • OR Immediate: • ori rt, rs, imm16 • LOAD and STORE Word • lw rt, rs, imm16 • sw rt, rs, imm16 • BRANCH: • beq rs, rt, imm16

  5. Logical Register Transfers • RTL gives the meaning of the instructions • All start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm16 = MEM[ PC ] inst Register Transfers ADDU R[rd] <– R[rs] + R[rt]; PC <– PC + 4 SUBU R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 STORE MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; PC <– PC + 4 BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4

  6. Step 1: Requirements of the Instruction Set • Memory • instruction & data • Registers (32 x 32) • read RS • read RT • Write RT or RD • PC • Extender • Add and Sub register or extended immediate • Add 4 or extended immediate to PC

  7. Step 2: Components of the Datapath • Combinational Elements • Storage Elements • Clocking methodology

  8. Combinational Logic Elements (Basic Building Blocks) CarryIn A 32 Sum 32 Adder B Carry • Adder • MUX • ALU 32 Select A 32 Y 32 MUX B 32 OP A 32 Result ALU 32 B 32

  9. Storage Element: Register (Basic Building Block) Write Enable Data In Data Out • Register • Similar to the D Flip Flop except • N-bit input and output • Write Enable input • Write Enable: • negated (0): Data Out will not change • asserted (1): Data Out will become Data In N N Clk

  10. Storage Element: Register File RW RA RB 5 5 5 Write Enable busA busW 32 32 32-bit Registers • Register File consists of 32 registers: • Two 32-bit output busses: busA and busB • One 32-bit input bus: busW • Register is selected by: • RA (number) selects the register to put on busA (data) • RB (number) selects the register to put on busB (data) • RW (number) selects the register to be writtenvia busW (data) when Write Enable is 1 • Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: • RA or RB valid => busA or busB valid after “access time.” 32 busB Clk 32

  11. Storage Element: Idealized Memory Write Enable Address Data In DataOut 32 32 • Memory (idealized) • One input bus: Data In • One output bus: Data Out • Memory word is selected by: • Address selects the word to put on Data Out • Write Enable = 1: address selects the memoryword to be written via the Data In bus • Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: • Address valid => Data Out valid after “access time.” Clk

  12. . . . . . . . . . . . . Clocking Methodology Clk Setup Hold Setup Hold Don’t Care • All storage elements are clocked by the same clock edge • Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew • (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time

  13. Step 3 • Register Transfer Requirements–> Datapath Assembly • Instruction Fetch • Read Operands and Execute Operation

  14. PC Clk Next Address Logic Address Instruction Memory 3a: Overview of the Instruction Fetch Unit • The common RTL operations • Fetch the Instruction: mem[PC] • Update the program counter: • Sequential Code: PC <- PC + 4 • Branch and Jump: PC <- “something else” Instruction Word 32

  15. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 3b: Add & Subtract • R[rd] <- R[rs] op R[rt] Example: addU rd, rs, rt • Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields • ALUctr and RegWr: control logic after decoding the instruction Rd Rs Rt ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32-bit Registers Result 32 ALU 32 busB Clk 32

  16. Register-Register Timing Clk Clk-to-Q Old Value New Value PC Instruction Memory Access Time Rs, Rt, Rd, Op, Func Old Value New Value Delay through Control Logic ALUctr Old Value New Value RegWr Old Value New Value Register File Access Time busA, B Old Value New Value ALU Delay busW Old Value New Value Rd Rs Rt ALUctr Register Write Occurs Here RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32-bit Registers Result 32 ALU 32 busB Clk 32

  17. 11 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits rd? 31 16 15 0 immediate 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 bits 16 bits 3c: Logical Operations with Immediate • R[rt] <- R[rs] op ZeroExt[imm16] ] Rd Rt RegDst Mux Rs ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 Result 32 32-bit Registers 32 ALU 32 busB Clk 32 Mux imm16 ZeroExt 32 16 ALUSrc

  18. 11 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits rd 3d: Load Operations • R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16 Rd Rt RegDst Mux Rs ALUctr RegWr 5 5 5 busA W_Src Rw Ra Rb busW 32 32 32-bit Registers 32 ALU 32 busB Clk MemWr 32 Mux Mux WrEn Adr Data In 32 Data Memory 32 imm16 32 Extender 16 Clk ALUSrc ExtOp

  19. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 3e: Store Operations • Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, rs, imm16 Rd Rt ALUctr MemWr W_Src RegDst Mux Rs Rt RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32-bit Registers 32 ALU 32 busB Clk 32 Mux Mux WrEn Adr Data In 32 32 Data Memory imm16 32 Extender 16 Clk ALUSrc ExtOp

  20. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 3f: The Branch Instruction • beq rs, rt, imm16 • mem[PC] Fetch the instruction from memory • Equal <- R[rs] == R[rt] Calculate the branch condition • if (COND eq 0) Calculate the next instruction’s address • PC <- PC + 4 + ( SignExt(imm16) x 4 ) • else • PC <- PC + 4

  21. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Cond Rs Rt 4 RegWr 5 5 5 busA Rw Ra Rb Adder busW 32 32 32-bit Registers Equal? Mux busB Clk PC 32 Adder Clk Datapath for Branch Operations • beq rs, rt, imm16 Datapath generates condition (equal) Inst Address nPC_sel 32 00 imm16 PC Ext

  22. Inst Memory Adr Adder Mux Adder Putting it All Together: A Single Cycle Datapath Instruction<31:0> <0:15> <21:25> <16:20> <11:15> Rs Rt Rd Imm16 RegDst nPC_sel ALUctr MemWr MemtoReg Equal Rt Rd 0 1 Rs Rt 4 RegWr 5 5 5 busA Rw Ra Rb = busW 00 32 32 32-bit Registers 0 32 ALU busB 32 0 PC 32 Mux Mux Clk 32 WrEn Adr 1 Clk 1 Data In Data Memory imm16 32 Extender PC Ext 16 imm16 Clk ExtOp ALUSrc

  23. Step 4: Given Datapath: RTL -> Control Instruction<31:0> Inst Memory <21:25> <0:15> <21:25> <16:20> <11:15> Adr Op Fun Rt Rs Rd Imm16 Control ALUctr nPC_sel MemWr MemtoReg ALUSrc RegWr RegDst ExtOp Equal DATA PATH

  24. Meaning of the Control Signals MemWr: write memory MemtoReg: 1 => Mem RegDst: 0 => “rt”; 1 => “rd” RegWr: write dest register • ExtOp: “zero”, “sign” • ALUsrc: 0 => regB; 1 => immed • ALUctr: “add”, “sub”, “or” RegDst ALUctr MemWr MemtoReg Equal Rt Rd 0 1 Rs Rt RegWr 5 5 5 busA = Rw Ra Rb busW 32 32 32-bit Registers 0 32 ALU busB 32 0 32 Mux Mux Clk 32 WrEn Adr 1 1 Data In Data Memory imm16 32 Extender 16 Clk ExtOp ALUSrc

  25. Adder Mux Adder Example: Load Instruction Instruction<31:0> Inst Memory <0:15> <21:25> <16:20> <11:15> Adr Rs Rt Rd Imm16 RegDst nPC_sel ALUctr MemWr MemtoReg Rt Equal Rd rt add +4 0 1 Rs Rt 4 RegWr 5 5 5 busA Rw Ra Rb = busW 00 32 32 32-bit Registers 0 32 ALU busB 32 0 PC 32 Mux Mux Clk 32 WrEn Adr 1 Clk 1 Data In Data Memory imm16 32 Extender PC Ext 16 imm16 Clk sign ext ExtOp ALUSrc

  26. PC ALU Clk An Abstract View of the Implementation Control Ideal Instruction Memory Control Signals Conditions Instruction • Logical vs. Physical Structure Rd Rs Rt 5 5 5 Instruction Address A Data Address Data Out 32 Rw Ra Rb 32 Ideal Data Memory 32 Next Address 32 32-bit Registers Data In B Clk Clk 32 Datapath

  27. Summary • 5 steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic • MIPS makes it easier • Instructions same size • Source registers always in same place • Immediates same size, location • Operations always on registers/immediates • Single cycle datapath => CPI=1, CCT => long • Next time: implementing control

  28. Instruction<31:0> nPC_sel Instruction Fetch Unit Rd Rt <0:15> <21:25> <16:20> <11:15> Clk RegDst 1 0 Mux Rt Rs Rd Imm16 Rs Rt RegWr ALUctr 5 5 5 MemtoReg busA Zero MemWr Rw Ra Rb busW 32 32 32-bit Registers 0 32 ALU busB 32 0 Clk 32 Mux 32 Mux 1 WrEn Adr 1 Data In 32 Data Memory imm16 32 Extender 16 Clk ALUSrc ExtOp Recap: A Single Cycle Datapath • We have everything except control signals (underline) • Today’s lecture will show you how to generate the control signals

  29. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits RTL: The Add Instruction • add rd, rs, rt • mem[PC] Fetch the instruction from memory • R[rd] <- R[rs] + R[rt] The actual operation • PC <- PC + 4 Calculate the next instruction’s address

  30. Inst Memory Instruction<31:0> Adr nPC_sel 4 Adder 00 Mux PC Adder Clk imm16 Instruction Fetch Unit at the Beginning of Add • Fetch the instruction from Instruction memory: Instruction <- mem[PC] • This is the same for all instructions PC Ext

  31. 31 26 21 16 11 6 0 op rs rt rd shamt funct The Single Cycle Datapath during Add Instruction<31:0> nPC_sel= +4 • R[rd] <- R[rs] + R[rt] Instruction Fetch Unit Rd Rt <0:15> <21:25> <16:20> <11:15> Clk RegDst = 1 1 0 Mux ALUctr = Add Rt Rs Rd Imm16 Rs Rt RegWr = 1 5 5 5 MemtoReg = 0 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 32 ALU busB 32 0 Clk 32 Mux 32 Mux 1 WrEn Adr 1 Data In 32 Data Memory imm16 32 Extender 16 Clk ALUSrc = 0 ExtOp = x

  32. Inst Memory Adr Adder Mux Adder Instruction Fetch Unit at the End of Add • PC <- PC + 4 • This is the same for all instructions except: Branch and Jump Instruction<31:0> nPC_sel 4 00 PC Clk imm16

  33. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Or Immediate Instruction<31:0> nPC_sel = • R[rt] <- R[rs] or ZeroExt[Imm16] Instruction Fetch Unit Rd Rt <0:15> <21:25> <16:20> <11:15> Clk RegDst = 1 0 Mux Rt Rs Rd Imm16 Rs Rt ALUctr = RegWr = 5 5 5 MemtoReg = busA Zero MemWr = Rw Ra Rb busW 32 32 32-bit Registers 0 32 ALU busB 32 0 Clk 32 Mux 32 Mux 1 WrEn Adr 1 Data In 32 Data Memory imm16 32 Extender 16 Clk ALUSrc = ExtOp =

  34. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Load Instruction<31:0> nPC_sel= +4 • R[rt] <- Data Memory {R[rs] + SignExt[imm16]} Instruction Fetch Unit Rd Rt <0:15> <21:25> <16:20> <11:15> Clk RegDst = 0 1 0 Mux ALUctr = Add Rt Rs Rd Imm16 Rs Rt RegWr = 1 MemtoReg = 1 5 5 5 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 32 ALU busB 32 0 Clk 32 Mux Mux 1 WrEn Adr 1 Data In 32 Data Memory 32 imm16 32 Extender 16 Clk ALUSrc = 1 ExtOp = 1

  35. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Store Instruction<31:0> nPC_sel = • Data Memory {R[rs] + SignExt[imm16]} <- R[rt] Instruction Fetch Unit Rd Rt <0:15> <21:25> <16:20> <11:15> Clk RegDst = 1 0 Mux Rt Rs Rd Imm16 Rs Rt ALUctr = RegWr = 5 5 5 MemtoReg = busA Zero MemWr = Rw Ra Rb busW 32 32 32-bit Registers 0 32 ALU busB 32 0 Clk 32 Mux 32 Mux 1 WrEn Adr 1 Data In 32 Data Memory imm16 32 Extender 16 Clk ALUSrc = ExtOp =

  36. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Store Instruction<31:0> nPC_sel= +4 • Data Memory {R[rs] + SignExt[imm16]} <- R[rt] Instruction Fetch Unit Rd Rt <0:15> <21:25> <16:20> <11:15> Clk RegDst = x 1 0 Mux ALUctr = Add Rt Rs Rd Imm16 Rs Rt RegWr = 0 5 5 5 MemtoReg = x busA Zero MemWr = 1 Rw Ra Rb busW 32 32 32-bit Registers 0 32 ALU busB 32 0 Clk 32 Mux 32 Mux 1 WrEn Adr 1 32 Data In Data Memory imm16 32 Extender 16 Clk ALUSrc = 1 ExtOp = 1

  37. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Branch Instruction<31:0> nPC_sel= “Br” • if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0 Instruction Fetch Unit Rd Rt <0:15> <21:25> <16:20> <11:15> Clk RegDst = x 1 0 Mux ALUctr = Subtract Rt Rs Rd Imm16 Rs Rt RegWr = 0 MemtoReg = x 5 5 5 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 32 ALU busB 32 0 Clk 32 Mux 32 Mux 1 WrEn Adr 1 Data In 32 Data Memory imm16 32 Extender 16 Clk ALUSrc = 0 ExtOp = x

  38. 31 26 21 16 0 op rs rt immediate Inst Memory Adr Adder Mux Adder Instruction Fetch Unit at the End of Branch • if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4 Instruction<31:0> nPC_sel 4 00 PC Clk imm16

  39. Step 4: Given Datapath: RTL -> Control Instruction<31:0> Inst Memory <21:25> <0:15> <21:25> <16:20> <11:15> Adr Op Fun Rt Rs Rd Imm16 Control ALUctr nPC_sel MemWr MemtoReg ALUSrc RegWr RegDst ExtOp Equal DATA PATH

  40. A Summary of Control Signals inst Register Transfer ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4” LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = “Br”, ALUctr = “sub”

  41. add sub ori lw sw beq jump RegDst 1 1 0 0 x x x ALUSrc 0 0 1 1 1 0 x MemtoReg 0 0 0 1 x x x RegWrite 1 1 1 1 0 0 0 MemWrite 0 0 0 0 1 0 0 nPCsel 0 0 0 0 0 1 0 Jump 0 0 0 0 0 0 1 ExtOp x x 0 1 1 x x ALUctr<2:0> Add Subtract Or Add Add xxx Subtract 31 26 21 16 11 6 0 op rs rt rd shamt funct immediate op rs rt op target address A Summary of the Control Signals See func 10 0000 10 0010 We Don’t Care :-) Appendix A op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type add, sub I-type ori, lw, sw, beq J-type jump

  42. op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type ori lw sw beq jump RegDst 1 0 0 x x x ALUSrc 0 1 1 1 0 x MemtoReg 0 0 1 x x x RegWrite 1 1 1 0 0 0 MemWrite 0 0 0 1 0 0 Branch 0 0 0 0 1 0 Jump 0 0 0 0 0 1 ExtOp x 0 1 1 x x ALUop<N:0> “R-type” Or Add Add xxx Subtract ALU Control (Local) The Concept of Local Decoding func ALUctr op 6 Main Control 3 ALUop 6 N ALU

  43. func ALU Control (Local) op 6 ALUctr Main Control ALUop 6 3 N The Encoding of ALUop • In this exercise, ALUop has to be 2 bits wide to represent: • (1) “R-type” instructions • “I-type” instructions that require the ALU to perform: • (2) Or, (3) Add, and (4) Subtract • To implement the full MIPS ISA, ALUop has to be 3 bits to represent: • (1) “R-type” instructions • “I-type” instructions that require the ALU to perform: • (2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi) R-type ori lw sw beq jump ALUop (Symbolic) “R-type” Or Add Add xxx Subtract ALUop<2:0> 1 00 0 10 0 00 0 00 xxx 0 01

  44. func ALU Control (Local) op 6 ALUctr Main Control ALUop 6 3 N R-type ori lw sw beq jump ALUop (Symbolic) “R-type” Or Add Add xxx Subtract ALUop<2:0> 1 00 0 10 0 00 0 00 xxx 0 01 31 26 21 16 11 6 0 R-type op rs rt rd shamt funct funct<5:0> Instruction Operation ALUctr ALUctr<2:0> ALU Operation 10 0000 add 000 Add 10 0010 subtract 001 Subtract 10 0100 and 010 And ALU 10 0101 or 110 Or 10 1010 set-on-less-than 111 Set-on-less-than The Decoding of the “func” Field Recall ALU Homework (also P. 286 text):

  45. R-type ori lw sw beq ALUop (Symbolic) “R-type” Or Add Add Subtract ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 ALUop func ALU Operation ALUctr bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> bit<2> bit<1> bit<0> 0 0 0 x x x x Add 0 1 0 0 x 1 x x x x Subtract 1 1 0 0 1 x x x x x Or 0 0 1 1 x x 0 0 0 0 Add 0 1 0 1 x x 0 0 1 0 Subtract 1 1 0 1 x x 0 1 0 0 And 0 0 0 1 x x 0 1 0 1 Or 0 0 1 1 x x 1 0 1 0 Set on < 1 1 1 funct<3:0> Instruction Op. The Truth Table for ALUctr 0000 add 0010 subtract 0100 and 0101 or 1010 set-on-less-than

  46. The Logic Equation for ALUctr<2> ALUop func bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<2> 0 x 1 x x x x 1 1 x x 0 0 1 0 1 • ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0> 1 x x 1 0 1 0 1 This makes func<3> a don’t care

  47. The Logic Equation for ALUctr<1> ALUop func bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<1> 0 0 0 x x x x 1 0 x 1 x x x x 1 • ALUctr<1> = !ALUop<2> & !ALUop<0> + ALUop<2> & !func<2> & !func<0> 1 x x 0 0 0 0 1 1 x x 0 0 1 0 1 1 x x 1 0 1 0 1

  48. The Logic Equation for ALUctr<0> ALUop func bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<0> 0 1 x x x x x 1 1 x x 0 1 0 1 1 • ALUctr<0> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0> 1 x x 1 0 1 0 1

  49. func ALU Control (Local) 6 ALUctr ALUop 3 3 The ALU Control Block • ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0> • ALUctr<1> = !ALUop<2> & !ALUop<0> + ALUop<2> & !func<2> & !func<0> • ALUctr<0> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

  50. RegDst func ALUSrc ALUctr ALU Control (Local) op 6 Main Control : 3 6 ALUop 3 The “Truth Table” for the Main Control op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type ori lw sw beq jump RegDst 1 0 0 x x x ALUSrc 0 1 1 1 0 x MemtoReg 0 0 1 x x x RegWrite 1 1 1 0 0 0 MemWrite 0 0 0 1 0 0 Branch 0 0 0 0 1 0 Jump 0 0 0 0 0 1 ExtOp x 0 1 1 x x ALUop (Symbolic) “R-type” Or Add Add xxx Subtract ALUop <2> 1 0 0 0 x 0 ALUop <1> 0 1 0 0 x 0 ALUop <0> 0 0 0 0 x 1

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