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Solar Probe Plus FIELDS Instrument Quarterly Digital Fields Board

Solar Probe Plus FIELDS Instrument Quarterly Digital Fields Board. DFB Development Status. DFB work proceeding well EM1 tested and characterization in-process Xilinx FPGA Daughter Board complete and integrated with EM1

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Solar Probe Plus FIELDS Instrument Quarterly Digital Fields Board

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  1. Solar Probe Plus FIELDSInstrument QuarterlyDigital Fields Board

  2. DFB Development Status • DFB work proceeding well • EM1 tested and characterization in-process • Xilinx FPGA Daughter Board complete and integrated with EM1 • EM2 development moving into layout, schematic review held last Friday, 6/13 • SIDECAR ASIC screening complete on FM parts, in-process on remaining EM part • FPGA development continues on remaining modules: Triggers, Burst Memory, and Spectra/Cross-Spectra • EEE Parts approved by PCB, and procurements nearing completion • All known orders for EM2 and FM complete, with most parts are in house • ASIC CGA attachment PO placed with BAE Systems • 1st article inspection ~ 5 weeks, Eng& QA on-site inspection • Three mechanical parts for vibe and ‘practice’ for board assembly; and one part for EM2 • After EM2 board assembly and testing, will turn-on attachment of two FM parts • Closed 7 of 8 Peer Review actions items, • 8th response in review by SPF team; no I-PDR or M-PDR action items assigned to DFB • Risk mitigation plans are proceeding and trending downward • ASIC screening confirms parts are viable flight candidates • Board deflection analysis indicates positive margin, vibration testing to confirm

  3. DFB Development Road Map SIDECAR Evaluation Board Prototype DFB Xilinx FPGA DB EM2 Schematic Review complete 6/13 Notional Layout Shown Flight DFB EM2-Flatsat FPGA DB • EMs and FM DFBs can accommodate all variations of FPGA DB: Xilinx, ProASIC, ProtoRTAX, FM RTAX EM1

  4. DFB EM1 • EM1 bench testing complete • FPGA testing and characterization of DFB (including ASIC) starting ASIC FPGA DB • FPGA DB with programmable Xilinx, upward compatible code with ProASIC/RTAX FPGAs • SIDECAR ASIC in a socket with PCB structural enhancement cap

  5. DFB FPGA DIAGRAM DBM Spectra & X-Spectra Spectra & X-Spectra

  6. DFB Test Lab Configurations SIDECAR ASIC Thermal Screening EM1 Testing Configuration DFB bench-level testing and characterization set-up • FPGA loads and science analysis continue for next couple months • ASIC characterization included • Thermal testing while EM2 is in layout/fab/assembly SIDECAR ASIC screening • Both FM and spare selected • Remaining EM part screening in-process

  7. DFB Schedule • Critical path is thru EMs • Reserve held @ 1mnth/year • Schedule threat is CGA attachment and EM2 assembly • Work-around is use of EM1 until EM2 is ready EM1 EM2

  8. DFB Backup slides

  9. Digital Fields BoardBlock Diagram Analog Filters / Gain stages 26 signals digitized @ 150 kS/s • Generates time domain • and spectral domain • data products (DC – 75kHz) • Implementation includes: • - Programmable gain states • Burst memory • Flexible configurations • Search coil cal. signal • Low mass, low power ADC 9 inputs: 5 E-field antennas 4 search coil channels FPGA processing

  10. DFB Risk Mitigation Proceeding If the SIDECAR experiences latent failure and/or has reliability issues, then the lack of a complete EIDP and respective workmanship could hinder the debug/troubleshooting, and have the potential to degrade performance and warrant possible redesign which could increase needed mass and power.Risk mitigationplan is to perform characterization and environmental testing on the SIDECARs. These parts have prior electrical burn-in testing hence characterization and environmental tests will demonstrate good rigor to retire the risk.  Risk rating: Probability 2, Impact 3; not likely to occur based on successful burn-in testing completed by GSFC/Teledyne; consequences slightly higher based on possibility of reverting to backup plan of discrete ADCs. Proposed/heritage ADCs are not as rad-tolerant, require more board space (mass increases), more power, and/or could drive science return. Newer, more viable, ADCs identified but require radiation testing. If the DFB PWBA experiences too high of structural deflection, then the assembled components may experience package stresses, with respective workmanship and/or reliability issues. The primary concern is the SIDECAR CGAs. This potential could warrant possible redesign of the PWB layout, structural stiffness design, or reduction in DFB capability due to replacing the SIDECAR/other components to stay within mass and power constraints. Analysis and part modeling in process now. Risk mitigationplan is to perform vibration testing to SPF-MEP vibration levels on an EM PWB with representative components and mass models.Analysis and modeling, along with vibration testing, must prove the PWBA design and demonstrate good rigor to retire the risk Risk rating: Probability 2, Impact 3; not likely to occur based on analysis and modeling and good design practices of the PWBA. Consequences now lowered with addition of ASIC Al cap which lowers structural deflection in areas of concern. Analysis complete, vibe test pre-CDR, cap in place on EM1.

  11. DFB Related Action Items DFB Peer Review held Nov 4-5th, materials available on SPF site Action Items from this and other Peer reviews included here (SCM Peer Review Sept 4-5, 2013) No DFB actions assigned at I-PDR or M-PDR

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