Motivation and Project Goals

1. Motivation and Project Goals • Goals: • Propose an efficient architecture for encoding and decoding of the LDPC codes, and prove its feasibility by implementing it on an FPGA. • Based on the FPGA implementation, gain insight into the behavior of the LDPC codes at very low error rates and propose novel constructions void of error floors.

2. Parity Check Matrix C1 C2 C3 C4 V1 V2 V3 V4 V5 V6 V7 V8 Tanner Graph V1 V2 C1 V3 C2 V4 V5 C3 V6 V7 C4 V8 Low Density Parity Check Code Representation

3. Decoding via Message Passing v1 bits to checks checks to bits bits to checks ….. hard decision (either all checks satisfied or initialize maxIter reached) c1 v2 …. v3 c2 c2→v4 v4→c2 …. v4 HD(v4)=1if =0 else c3 v5 …. c4→v4 v4→c4 v6 c4 v7 …. v8

4. Construction Shorten a Reed-Solomon code (n=q-1,k=q-r+1) into Cb by preserving only the last two information symbols. Construct Cb(1) as a subcode of Cb containing all multiples of a c in Cb whose weight is r. Properties By construction, there are no cycles of length 4 and the minimum distance is large. Each row of H has weight r. Each column of H has weight c. No error floors observed. 3. Partition the resulting code Cb into cosets of Cb(1) ; Cb(2), …, Cb(q). 4. For each coset Cb(j), define a matrix Aj whose rows are symbol locators of elements in Cb(j). 5. The resulting parity check matrix is H = [A1… Ac]t Example: n = 240, m = 8, r = 15, c = 5 An Example: RS-based LDPC* *[I. Djurdjevic, IEEE Comm. Letters, Jul. 2003]

5. Error Floors • Flattening of a BER-SNR “waterfall” curve occurs beyond the reach of a simulation. • Usually due to the so-called “near-codewords”, “trapping sets”, etc. • Lack of an analytical tool for describing error floors for different channels necessitates the FPGA implementation. Simulation and error floor predictions for regular (3,6) LDPC codes From top: Margulis graph (n=2640), an n=2048 code, an n=2640 code, and an=8096 code [T. Richardson, Allerton 2003]

6. Check and Bit Node Implementation • Using log-domain simplification, node implementations can be simplified. • Check node: Look up – add – subtract (marginalize) – Look up. • Bit node: add – subtract (marginalize). • Good coding performance can be achieved with arithmetic precision of 3-5 bits only. • Lookup table can be implemented in simple combinatorial logic. • Iteration is terminated when a preset threshold is reached. [E. Yeo, B. Nikolic, and V. Anantharam, IEEE Comm. Magazine, Aug. 2003]

7. Fully Parallel Architectures Direct-mapped architecture using an interconnect fabric Interconnects can be simplified by exploiting the structure of the code construction

8. Partially Parallel Architecture Partition the H matrix into regularly structured groups by choosing H that consists of stacked permutation sub-matrices Parallel process among multiple groups and serial process checks inside the group Line up check node (horizontal) and bit node (vertical) groups

9. Future Research • Code construction • Experiment with existing code constructions and investigate the nature of error floors. • Architectural exploration • Flexible and efficient architecture which allows for fast prototyping of different code constructions. • Error floor simulation • Real-time hardware emulation of codes to verify BER performance.