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Combating Bit Errors in Flash Memory using Information Theory Techniques

This paper explores a solution to mitigate the impact of stuck cells in flash memory using novel information theory techniques. By handling stuck cells during write time, the proposed solution eliminates the need for read-time solutions, improving quality of service (QoS) without incurring read-time penalties. Experimental results demonstrate the effectiveness of the proposed approach in reducing the impact of stuck cells.

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Combating Bit Errors in Flash Memory using Information Theory Techniques

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  1. Combating Bit Errors From Stuck Cells in Flash MemoryUsing Novel Information Theory Techniques Ravi Motwani, Zion Kwok, Poovaiah Palangappa NVMW 2018

  2. Outline • Problem: • Stuck cells are bad for LDPC codes • Read-time solutions are bad for QoS • Solution: • Write-time data encoding for handling stuck cells • Results

  3. Stuck cells impact high confidence bucket Low Confidence 0 Low Confidence 1 Medium Confidence 0 Medium Confidence 1 High Confidence 0 High Confidence 1 L1 L0 Logical bit 1 Logical bit 0 Threshold Voltage Stuck cells are High Confidence 0s

  4. Impact of stuck cells in 3d nand • SBR performance degradation

  5. Existing solutions in literature • By code construction • Heegard et. al. • Overhead increases as probability of opens increases • PAYG, ECP, etc. • Handling stuck cells by storing error correction pointers • Dynamically allocated • QoS impact due to reads from another NAND die/memory

  6. Handling Opens during read Vwlrvmax • Assume a SDD ECC fatal • Perform a SDD decode with extra sensing at Vwlrvmax • Open circuits will read as very high confidence logical-0 (VHC0) bits • LDPC decoder considers the VHC0 as erasures L0 L1

  7. Errors and erasures decoding of LDPC codes • Errors and erasures decoding gives close to regular SDD performance • Impacts the QoS due to the special SDD read with extra sensing

  8. Errors and erasures decoding of LDPC codes • Errors and erasures decoding gives close to regular SDD performance • Impacts the QoS due to the special SDD read with extra sensing Can we handle stuck cells during write instead?

  9. Solution Proposal • Handle stuck cells in the encoder • Incurs write-time penalty • No read-time penalty • We need: • Stuck-cells locations during encoding • Prior to write, a sensing at suitable read reference to identify opens in the band • Redundant bits to explicitly handle stuck cells

  10. Solution discussion • Total RBER has two components • Vtdistributions overlap, call this 𝑅𝐵𝐸𝑅_𝑉𝑡 • Stuck cells • Total RBER = 𝑞/2 + 𝑅𝐵𝐸𝑅_𝑉𝑡 • 𝑞, is the probability of a bit being a stuck cell

  11. Solution discussion • Total RBER has two components • Vtdistributions overlap, call this 𝑅𝐵𝐸𝑅_𝑉𝑡 • Stuck cells • Total RBER = 𝑞/2 + 𝑅𝐵𝐸𝑅_𝑉𝑡 • 𝑞, is the probability of a bit being a stuck cell Divide and conquer

  12. Solution discussion • Total RBER has two components • Vtdistributions overlap, call this 𝑅𝐵𝐸𝑅_𝑉𝑡 • Stuck cells • Total RBER = 𝑞/2 + 𝑅𝐵𝐸𝑅_𝑉𝑡 • 𝑞, is the probability of a bit being a stuck cell Data transformation for opens Divide and conquer

  13. Solution discussion • Total RBER has two components • Vtdistributions overlap, call this 𝑅𝐵𝐸𝑅_𝑉𝑡 • Stuck cells • Total RBER = 𝑞/2 + 𝑅𝐵𝐸𝑅_𝑉𝑡 • 𝑞, is the probability of a bit being a stuck cell Data transformation for opens LDPC for errors due to Vt overlap Divide and conquer

  14. Data Transformation Encoded data Stuck cell

  15. Flip-N-Write Data cells [1] S. Cho et al, “Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance,” MICRO, 2009

  16. Flip-N-Write Data cells Conflict × [1] S. Cho et al, “Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance,” MICRO, 2009

  17. Flip-N-Write Data cells Conflict × Flipped Data cells [1] S. Cho et al, “Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance,” MICRO, 2009

  18. Flip-N-Write Data cells Conflict × Flipped Data cells Agreement  [1] S. Cho et al, “Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance,” MICRO, 2009

  19. Sectionalized FNW payload parity Baseline • The payload is divided into 𝑚 sections • FNW encoding is performed for each section • The 𝑚 FNW flag bits are then appended with the data and encoded by the LDPC encoder • Parity is unprotected from opens FNW (payload) parity With FNW

  20. Impact on LDPC rate • Since FNW uses flag bits, the LDPC code becomes weaker by m • RBER degradation due to the weak code • Transformed data works on a lower RBER channel • Let 𝑝 be the probability of opens errors post FNW encoding, 𝑝 < 𝑞/2 • Total RBER = 𝑝 + 𝑅𝐵𝐸𝑅_𝑉𝑡

  21. Simulation Results • Restores the SDD performance

  22. Performance Impact • Prep stage: • Read a page at Vwlrvmaxreference voltage • Save the open locations • May need to update the opens locations periodically • While programming • Read the saved open locations being programmed

  23. Summary • Handling opens during reads • Data transformation to reduce contention between data and open-reads • A few overhead bits take care of opens • Opens information gathered as background operation • Lesser QoS impact

  24. Thank you

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