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OCP 3.0 Debug Power Management

OCP 3.0 Debug Power Management. Advanced Power Management challenges How to develop Power Aware debug systems How to debug power management issues How to prevent power management from complicating debug How can we leverage and integrate with relevant standards. Neal Stollon HDL Dynamics

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OCP 3.0 Debug Power Management

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  1. OCP 3.0 Debug Power Management Advanced Power Management challenges • How to develop Power Aware debug systems • How to debug power management issues • How to prevent power management from complicating debug • How can we leverage and integrate with relevant standards Neal Stollon HDL Dynamics neals@hdldynamics.com

  2. Debug of Power Aware OCP Systems • Clusters of power aware subsystems are the norm • OCP 3.0 adds power aware features • Debug integration must reflect the power aware environment

  3. Many Groups addressing the power issue • Power Control considerations for JTAG based debug • JTAG typically uses separate clock (TCK) and reset from rest of chip • Debug operations typically require both TCK and system clocks • OCP defines a FSM based Power Down Sequence for each Master. • Many masters, each with power schedules, adds complexity of analysis • Looking to standards to provide debug power management schemes • As an example in IEEE1149.7 standard, 4 JTAG power control modes defined • Allow power down if TCK a logic 1 for more than 1 millisecond • Allow power down if TCK a logic 1 for more than 1 millisecond AND in the Test-Logic-Reset TAP controller state • Allow power down if in the Test-Logic-Reset TAP controller state - • Always powered

  4. OCP (Power) Operations • Master may have primary (datapath) and debug interfaces • Each OCP Master/slave has a Power Management FSM • OCP Debug logic should power down in most normal operations • Other situations may require debug block to be active even if core and system clocks are powered down OCP master power FSM OCP power control

  5. OCP Debug Integration Options • From connection pov, Debug Socket may be instantiated different ways • Integrated with Master Port + Allows independent Power down sequence when not used. + Debug operations occur independently of other concurrent operation - Additional logic overhead associated with OCP Master • Alternate Master Socket + ongoing debug activity can stall power down sequence - Power down does not occur unless entire Master powers down • Slave Socket + Simple, allows some debug (triggering as example) operations in conjunction with the master - Relies on a Master to determine power down • Debug Block Power control should be integrated solution • Mode selection may be set by JTAG or processor accessible setup registers • TCK status may be externally monitored from JTAG return clock (RTCK)

  6. OCP 3.0 Debug – Work In Progress • Debug Power integration has issues that will be faced in many emerging SoC Architectures • Debug features and power management are architecture specific • OCP Debug Specification provides a general and customizable template • Need to integrate with power management features of OCP 3.0 AND other standards For more Information, contact: Neal Stollon HDL Dynamics neals@hdldynamics.com

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