System On Chip Verification Solution

1. System On Chip Verification Solution Gregor Siwinski Director of R&D Aldec, Inc.

2. Traditional SoC Process • Separate Hardware and Software development teams • Software integration testing is started late when hardware prototype is ready • Bugs are detected late in the process • Verification and bug fixes take majority of the design cycle HardwareSimulation HardwareDesign Prototype IntegrationTesting Specification SoftwareDesign SoftwareTesting

3. Software PROCESSOR MEMORY DRAM INTERFACE DMA BUSMASTER Embedded System Architecture DISPLAY BRIDGE UART PIO The software content is increasing. A system-on-a-chip designed today typically runs an operating system and some user applications.

4. Testbench Testbench RTL Code RTLCode Embedded Software ! SoC VERIFICATION CHALLENGES Embedded System Development Hardware System Development

5. Hardware Team requires: Accuracy at the bus level HDL debugging environment Performance Software Team requires: Software debugging environment High performance to execute large chunks of code    KEYPAD   BRIDGE UART 100instr./s SOFTWAREDEBUGGER PROCESSOR MEMORY not available PIO EXTERNAL MEMORY INTERFACE DMA BUSMASTER SoC Verification in HDL Simulator TYPICAL HDLSIMULATIONENVIRONMENT HDLDebugger

6. Emulation and Prototyping • Emulators and prototyping systems allow running the design at high speed along with the software programs • Emulation requires a significant cost • Compiling designs is a very tedious process due to FPGA partitioning and timing changes • Very low visibility for hardware debugging • Changes are very time consuming • Not possible to run behavioral testbench

7. Aldec SoC Development Solution Hardware Prototyping Board DEV3 Processor CORE DEV4 Software Development System and Debugger PCI Debugging Riviera Simulation TB DEV1 DEV2

8. Hardware Team requires: Accuracy at the bus level HDL debugging environment Performance Software Team requires: Software debugging environment High performance to execute large chunks of code    KEYPAD   BRIDGE UART PROCESSOR MEMORY PIO EXTERNAL MEMORY INTERFACE DMA BUSMASTER Accelerated SoC Simulation System SoftwareDebugger HDLDebugger

9. Compiling HDL into Hardware • Design Verification Manager • - Implements Incremental Prototyping • - Manages block insertion into Hardware board • - Applies a testbench to the implemented design

10. Benchmark Design • Image Processing design with processor and DSP

11. Sample Design Benchmarks Time [s] 1.3 Million gates

12. Software Debugging Environment • Software Debuggers connect to the CPU via TCP/IP interface • Programs can be preloaded to memory and executed in trace more or at full speed • Supported Debuggers: GDB, WindRiver, GreenMountain • Supported Processors: ARM, MIPS, PowerPC, Microblaze, NIOS, 8051

13. Co-Verification Performance Levels Simulation Acceleration 10X-100X Emulation 100K CPS- 1 M CPS 10X to 1 Million X over simulation Co-Verification1K to 100k CPS10,000X over simulation The Fastest!

14. Hardware Boards - PCI 33/66 MHz standards supported - Up to 12 million FPGA gates on board - Number of boards is limited by number of PCI slots - External memories - Daughter Board connectors Daughter Boards - The board architecture allows direct “attachment” of custom ICs such as RAM or MPU to designs residing in FPGAs. - Designers can use real CPU, ASIC or Memory devices instead of their simulation models.

15. Complete Accelerated Simulation • SOC software/hardware simulation with acceleration • Seamless integration with software tools • Complete debugging capabilities