Packaging of parallel optical interconnects modules with on chip optical access

1. Packaging of parallel optical interconnects modules with on chip optical access François Marion / Julien Routin (LETI) Ronny Bockstaele / Olivier Rits (IMEC)

2. Summary • Packaging for today • Flip chip technology • BGA package • Alignment techniques for fiber connector • Packaging for the future • CSP package development • Flip/chip over glass sheet PCB Packaged CMOS chips with direct on chip optical access PCB Optical pathways Optical pathways backplane DTA Digital technology assessment testbed

3. Mechanical interface Packaging for today Packaging specifications Packaging specifications • Electrical interface 296 I/O’s, LVDS signals • Optical interface 64 optical in, 64 optical out • Mechanical interface alignment of fiber connector : +/-5µm • Thermal interface 10W thermal dissipation • Hermeticity semi-hermetic packaging Optical connector Semi-hermetic package Optical IN Optical OUT Electrical I/O's PACKAGED chip PCB Ambiant Thermal dissipation Thermal sink

4. Packaging for today Packaging specifications DESIGN 296 electrical I/Os Thermal sink 10W 64 optical outputs 64 optical inputs +/-5µm mechanical guide

5. Packaging for today Packaging specifications FINAL PACKAGE

6. Packaging for today Packaging specifications DIFFERENT TASKS Develop reliable flip-chip technology for direct coupling of large arrays opto-chips on CMOS Provide alignment aids for optical connector passive alignment Provide custom BGA package

7. DTA1 CMOS Bumps for glass board F/C DESIGN FINAL Bumps for opto chips F/C Bumps for silicon benches F/C Bumped CMOS chip Packaging for today Develop flip chip technology : wafer bumping

8. Packaging for today Develop flip chip technology : wafer scale hybridization

9. Bump CMOS Hybridize VCSEL + photodiode chips Underfill 50µm THIN for butt coupling F/C optos and µbench on DTA1 CMOS bench Antireflective coating PIN detector VCSEL Dicing + hybridize Alignment plate bench Packaging for today Develop flip chip technology : wafer scale hybridization Post-process on CMOS wafer System on CHIP

10. Packaging for today Provide BGA package CUSTOM BGA PACKAGE

11. Provide BGA package Packaging for today SnPb bumps (302) Thermal sink Low speed I/O’s Controlled geometry X,Y Z High speed I/O’s (diff pairs)

12. Develop alignment technique Packaging for today Silicon bench alignement INDEX alignement

13. Packaging for today Develop silicon bench alignment technique Silicon bench for X,Y,Z alignment Guiding pins +/- 5µm X,Y misalignment versus optos

14. Packaging for today Develop silicon bench alignment technique AssemblageIO.exe

15. CMM measuring head Spacer plate on (X,Y,Z,a) stage Package on (,g) stage Assembly of the package using index alignment INDEX ALIGNMENT • Alignment is based on measurement of coordinates, not based on mechanical contact • Then attach using UV-curable adhesive

16. Direct hybridization of CMOS+opto on customized CSP ceramic CSP package CMOS + optos To PCB Optics in pathway • Package size reduced to 15*15mm (vs. 26*28mm for « today BGA ») • Alignment pins placement made easier • NO wirebonds (increased speed) • Optics included in pathway = • connector made easier • optical coupling made easier • hermeticity made easier Packaging for tomorrow CSP package New concept CSP package

17. Copper traces (Electronic) Optical waveguides (photonic) Silicon CMOS Electrooptical PCB Glass waveguide Packaging for tomorrow Chip on optical (glass sheet) board • ULTIMATE : direct flip chip over glass sheet PCB

18. CONCLUSION • Conclusion : • Packaging for to-day = first packaged modules delivered • Packaging for tomorrow = development on going: • CSP (chip scale packaging) • Chip On Board packaging (glass sheet board)