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RTL for MIPS instructions

RTL for MIPS instructions. Fall 2005-2006. add. PC = PC + 4; IR = Mem[PC] A = Reg[IR[25:21]]; B = Reg[IR[20:16]]; Sum = PC + SE[IR[15:0]]<< 2 if((IR[31:26] == 0) && (IR[5:0] == 32)) then 3. Sum = A + B 4. Reg[IR[15:11]] = Sum. lw. PC = PC + 4; IR = Mem[PC]

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RTL for MIPS instructions

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  1. RTL for MIPS instructions Fall 2005-2006

  2. add • PC = PC + 4; IR = Mem[PC] • A = Reg[IR[25:21]]; B = Reg[IR[20:16]]; Sum = PC + SE[IR[15:0]]<< 2 if((IR[31:26] == 0) && (IR[5:0] == 32)) then 3. Sum = A + B 4. Reg[IR[15:11]] = Sum

  3. lw • PC = PC + 4; IR = Mem[PC] • A = Reg[IR[25:21]]; B = Reg[IR[20:16]]; Sum = PC + SE[IR[15:0]]<< 2 if((IR[31:26] == 35) then 3. Sum = A + SE[IR[15:0]] 4. MDR = Mem[Sum] 5. Reg[IR[20:16]] = MDR

  4. sw • PC = PC + 4; IR = Mem[PC] • A = Reg[IR[25:21]]; B = Reg[IR[20:16]] if((IR[31:26] == 43) then 3. Sum = A + SE[IR[15:0]]; B = Reg[IR[20:16]] 4. Mem[Sum] = B Sum = PC + SE[IR[15:0]]<< 2

  5. beq • PC = PC + 4; IR = Mem[PC] • A = Reg[IR[25:21]]; B = Reg[IR[20:16]] Sum = PC + SE[IR[15:0]]<< 2 ; if((IR[31:26] == 4) then 3. If (A – B == 0) then PC = Sum

  6. j • PC = PC + 4; IR = Mem[PC] • A = Reg[IR[25:21]]; B = Reg[IR[20:16]]; Sum = PC + SE[IR[15:0]]<< 2 if((IR[31:26] == 2) then 3. PC = PC[31:28] || IR[25:0] || 00

  7. jal • PC = PC + 4; IR = Mem[PC] • A = Reg[IR[25:21]]; B = Reg[IR[20:16]]; Sum = PC + SE[IR[15:0]]<< 2 if((IR[31:26] == 3) then 3. PC = PC[31:28] || IR[25:0] || 00Reg[31] = PC

  8. jr • PC = PC + 4; IR = Mem[PC] • A = Reg[IR[25:21]]; B = Reg[IR[20:16]]; Sum = PC + SE[IR[15:0]]<< 2 if((IR[31:26] == 0 and IR[5:0] == 8) 3. PC = A

  9. Single-cycle datapath • Simple control unit (combinational logic) • The processor will be under-utilized (idle during portions of the clock cycle for many instructions)

  10. add PC = PC + 4 If ( (Mem[PC])[31:26] == 0 && (Mem[PC])[5:0]) == 32) then Reg[ (Mem[PC])[15:11]] = Reg[(Mem[PC])[25:21]] + Reg[(Mem[PC])[20:16]]

  11. lw PC = PC + 4 If ( (Mem[PC])[31:26] == 35) then Reg[ (Mem[PC])[20:16]] = Mem [ ] Reg [ ] (Mem[PC])[25:21] + SE[ ] (Mem)[PC][15:0]

  12. sw PC = PC+4 If((Mem[PC])[31:26] == 43) then Mem[Reg[(Mem[PC])[25:21]] + SE[(Mem[PC]) [15:0]] ] = Reg[ (Mem[PC])[20:16]]

  13. beq PC = PC + 4 If ( (Mem[PC])[31:26] == 4) then if( (Reg[(Mem[PC])[25:21]] – Reg[(Mem[PC])[20:16]) == 0) then PC = PC + [SE[(Mem[PC])[15:0] << 2]

  14. j PC = PC + 4 If ( (Mem[PC])[31:26] == 2) then PC = PC[31:28]|| (Mem[PC])[25:0] || 00

  15. lui PC = PC + 4if((Mem[PC])[31:26] == 0xf) Reg[ (Mem[PC])[20:16] ] = (Mem[PC])[15:0] << 16

  16. addi PC = PC + 4if((Mem[PC])[31:26] == 0x8) Reg[ (Mem[PC])[20:16] ] = Reg[ (Mem[PC])[25:21] ] + SE[ (Mem[PC])[15:0] ]

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