Probabilistic CMOS & Probabilistic Boolean Logic

1. Probabilistic CMOS & Probabilistic Boolean Logic Zheng-Shan Yu & Ching-Yi Huang & Fox 2013/01/21

2. Outline • PCMOS • CMOS with noise • CMOS with varying voltages • Correctness v.s. energy • PBL • Previous work • Research direction • Future work

3. CMOS with noise • NOT:

4. CMOS with noise (cont.) • Interconnection noise • Simultaneous switching noise • Crosstalk • Thermal noise

5. CMOS with noise (cont.) • Noise models of PCMOS:

6. CMOS with varying voltages With noise Add noise Without noise Raise voltage to avoid noise

7. Correctness v.s. energy • Energy per switching: Energy ratio p

8. Probabilistic Boolean logic • Probabilistic OR: ∨p • Probabilistic AND: ∧p • Probabilistic NOT: ¬p • Example: ∨p , assume p=0.9

9. Probabilistic Boolean logic • A probabilistic Boolean formula & circuit • F = (a ∧0.8 b)∨0.7(¬0.8c) a n 0.8 b 0.7 F 0.8 c m

10. Probabilistic Boolean logic (cont.) • OR: Pout = (1–Pa)*(1–Pb)*(1–p) + [1–(1–Pa)*(1–Pb)]*p • AND: Pout = Pa*Pb*p + (1 – Pa*Pb)*(1–p) • NOT: Pout= (1–Pin)*p + Pin*(1–p) Pa Pout p Pb Pa Pout p Pb p Pout Pin

11. Probabilistic Boolean logic (cont.) • F = (a ∧0.8 b)∨0.7(¬0.8c) • P(n) = 1*1*0.8 + 0*0*0.2 = 0.8 • P(m) = 0*0.8 + 1*0.2 = 0.2 • P(F) = 0.2*0.8*0.3 + (1-0.8*0.2)*0.7 = 0.636 1 n 0.8 1 0.7 F 0.8 1 m

12. Probabilistic Boolean logic (cont.) • F = (a ∧0.8 b)∨0.7(¬0.8c) • When (AND,NOT,OR) = (C,C,C) (C,I,C) (I,I,C) (I,C,I), F=1 • The probability of each situation 0.448, 0.112, 0.028, 0.048 • P(F=1) = 0.636 1 n 0.8 1 0.7 F 0.8 1 m

13. Previous work • A Statistics Approach to Correctness Analysis for Probabilistic Boolean Circuits • Problem formulation: • Given a probabilistic Boolean circuit and an input pattern • Report the output probabilities of correctness • Monte Carlo Method • Random Pattern Generation • Sampling Rule • Scoring • Error Estimation

14. Previous work (cont.) • Monte Carlo simulation • simulate until reaching the stop point RPG 1 n 0.8 1 0.7 F 0.8 1 ‧ ‧ ‧ m ‧ ‧

15. Research direction • Problem formulation 1: • Given a deterministic Boolean circuit and a correctness constraint • Report a low-energy-consumption probabilistic Boolean circuit satisfying the correctness constraint Low power & Correctness >N Required Correctness >N Our program ///////////////////////////////////////////////////////////////////////////

16. Research direction (cont.) • Problem formulation 2: • Given a deterministic Boolean circuit and an energy constraint • Report a high-correctness probabilistic Boolean circuit satisfying the energy constraint High correctness & energy consumption <N Required energy consumption <N Our program ///////////////////////////////////////////////////////////////////////////

17. Research direction (cont.) • Correctness • If the correct value at the output under an input pattern is 0 • c i= 1 – p1i • If the correct value at the output under an input pattern is 1 • c i= p1i • For all n input patterns • Average correctness =

18. Research direction (cont.) • Function control • Assign probability parameters • Add side inputs • Issue • Which gates are good choices to assign? • Which probabilities should be assigned? Add p 0.9 Add a side input 0.8 0 0.9 0.9

19. Research direction (cont.) A x C y • Assign probability parameters • Low testability B 0.9 F z A x 0.9 C y B F z

20. Research direction (cont.) • Energy control • Basic energy consumption • Issue • Load capacitance changes in different manufacture processes. Static power? Per switching? 0.9 0.8

21. Future work • Function control • Testability • Benefits of adding a side input • Output probabilities under all input patterns • More… • Energy control • Energy consumption of a basic probabilistic Boolean gate • Hspice • Cell libraries • More…