Xilinx Alliance Series

1. Xilinx Alliance Series Powerful High Density Solutions Integrated into Your EDA Environment http://www.xilinx.com/products/alliance.htm

2. Higher Densities & PerformanceRequires Powerful Software Virtex 1M+ Systems Gates System Solution 0.25/0.18µ 2.5/1.8 Volt XC4000XV Largest Device 500,000 sys. gates 0.25m 2.5 Volt 30% Faster than XL Density/Performance XC4000XL Largest Device 180,000 sys. gates 0.35m 3.3 Volt 30% faster than EX XC4000EX Largest Device XC4036EX 0.5m 5 Volt 30% faster than E 1 Million Gates in 1998 XC4000E Largest Device XC4025E 0.5m 5 Volt Year 1995 1997 1998 1999 1996

3. TheAlliance Series Advantage Only Xilinx delivers these essential capabilities • Powerful timing-driven technology & graphical Constraints Editor • Highest performance with industries leading synthesis vendors • Dramatic productivity improvements with the Core Generator • Support for industries highest density FPGA XC40250XV 500K system gates • Guarantee your design performance with min & max timing

4. Expanding the Leadership The latest Xilinx software delivers • Support for the industry’s 1st 1M gate FPGA Designs • The industries fastest timing-driven compile times • 50% faster compile times • Max Design performance: AKAspeedtmtechnology • Up to 30% faster performance • Higher productivity with HDL Simulators Model Technology Eval in the Box • Web-enabled design tools

5. Performance Based DesignTiming Driven Technology • Maximum Device Performance • Achieve max design performance: AKAspeedtmtechnology • Robust timing constraints language, SMARTspecs • 40% Higher Performance with the Floorplanner • Xilinx Core Generator • Industry’s Fastest Devices • Highest Area Utilization Available • > 95% Device Utilization • Flexibility • Freedom to choose the most cost effective device • Design changes with repeatable performance

6. Achieve Maximum Performance with AKAspeedtm Technology • Minimum delays • Voltage and temperature prorating • Graphical constraints editor • Graphical Floorplanner • Integration with CORE Generator New Algorithms Features • Timing-driven implementation K-paths • Advanced timing analysis algorithms • Robust timing language • Incremental Designing • Cores Enhancements to v1.4 Optimized for Today’s Higher Performance Higher Density Designs

7. Flexibility Provides a Productivity Edge • Flexibility • Freedom to choose the most cost effective device • Design changes with repeatable performance • Easy to track design change with revision control • Instant software access with registration-based security • Extensive Platform/OS Support • Win95, WinNT 4.0, NEC PC98 • Chinese, Korean & Japanese Windows • Solaris 2.5 & 2.6, HP-UX 10.2, IBM RS6000 AIX 4.1.5 • CDE

8. Constraint Entry Made Easier • Guides user to the best constraint methodology • Eliminates need for user knowledge of syntax • Reduces need for user knowledge of design nets & components

9. Floorplanner • Specify physical placement to reduce routing delays & increase performance up to 40% • Area constraints for modules provide • faster runtimes • higher performance • design changes made easier

10. Web-enabled Design Tools • Integrated into Design Manager • Instant Access to http://support.xilinx.com • Netscape and MS Explorer compatible News Bulletins Searchable Knowledge Base(includes agent reports) Designer Tools & Services

11. Simulation Synthesis Simulation Simulation Alliance Series Flow Schematics Cores HDL • Powerful yet simple HDL design flow • Fits into ASIC flow • Enables multiple sources & multiple EDA vendors in the same flow • Simulate anywhere in the design flow • Design the way you are used to! EDIF, VHDL Verilog, SDF Device Implementation

12. The Value of PartnershipsThe most comprehensive “Open System” solution • Early software support for new devices • New product development maximizing architectural and synthesis capabilities • Efficient timing constraints integration • High performance optimization engines tuned for new Xilinx devices • Direct optimization & mapping of Carry logic, complex I/O, LUTs, CE, arithmetic operator • Joint definition of next-generationdesign flows and technology

13. HDL VerificationWe will take you to the leaders • Why simulate? • Reduce time-to-market 25% • Errors early in the design cycle (RTL) are inexpensive to fix • Bottom up and team design for large designs require each module to be verified • It takes twice as long to isolate a bug in hardware than in simulation • Xilinx will take you to the leaders • Visit our HDL Verification Website for our premier partners, articles & design guides http://www.xilinx.com/products/alliance/verifi.htm

14. Bus Interface Memory Interface DMA Module High PerformanceReduce Design Time Cores are essential to High Density Designs • General purpose delivery vehicle for IP • Predictable & repeatable • Independent of device size • Constant performance as more cores are added • Advance specification • Compatible with HDL Design Flows Custom Design App Specific Module Processor

15. Alliance SeriesLeading Xilinx into Year 2000 • Alliance Future • New Device Families • Reduced Runtimes • Ease of Use • Enhanced Synthesis QOR • Core Generator Enhancements • Modular & Team Design Enhancements • Guide for Synthesis • HDL + Cores + ASIC tools 2M Gates • Alliance 2.1 • New Device Families • Reduced Runtimes • Ease of Use • Enhanced Synthesis QOR & Flows • Modular & Team Design • Guide for Synthesis • Enhanced Core Generator Integration • Improved HDL Verification Flows • System Verification Support • HDL + Cores + ASIC tools 1M Gates Features and Enhancements 1999 2000

16. $95! Upgrade Options Software Support Choice Path Maintenance Software that Makes a Difference Base Configurations DS-ALI-BAS-PC $495 DS-ALI-BAS-WS $750 Standard Configurations DS-ALI-STD-PC $3995 DS-ALI-STD-WS $5995 Evaluation DS-ALI-EVAL

17. Appendix

18. Core Delivery Mechanism, In Your Flow SystemLINX Call the CORE Generator from third-party tools Access more Cores from our Partners Data sheets CoreLINX: Download new cores from the WEB! Cores available from Xilinx DSP, PCI, general purpose

19. CPLD Implementation Flow • Simplified Project Management • Implementation Templates for Speed & Density • Push Button Design Flows Performance algorithm enhancements ensure faster clock speeds,higher device utilization and the industry’s best pin-locking capabilities!