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VLSI Project Presentation

VLSI Project Presentation. CMOS Phase Locked Loop Group Members: Louis and Yucong. Phase Locked Loop Block Diagram. Ring Oscillator. CMOS ring oscillator requires odd number of inverters in series to introduce a feedback that cause output switching between 0 and 1. CMOS Implementation

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VLSI Project Presentation

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  1. VLSI Project Presentation CMOS Phase Locked Loop Group Members: Louis and Yucong

  2. Phase Locked Loop Block Diagram

  3. Ring Oscillator CMOS ring oscillator requires odd number of inverters in series to introduce a feedback that cause output switching between 0 and 1.

  4. CMOS Implementation for 3-stage ring oscillator starved current source

  5. Transient Simulation of Ring Oscillator Control Voltage = 900mV, Frequency = 22.2GHz

  6. Frequency Phase Detector

  7. Frequency Phase Detector CMOS implementation for high speed applications. It has free dead zone and more sensitive behavior.

  8. Charge Pump and Loop Filter

  9. Charge Pump and Loop Filter • Size PMOS and NMOS same to ensure identical current. • Use high order loop filter to stabilize charging/discharging response time.

  10. PLL in Cadence without Frequency Division

  11. Transient Simulation of 20GHz Reference Signal

  12. Frequency Divider with D Flip Flop

  13. Frequency Divider - CMOS Implementation

  14. PLL with Frequency Division 1/64 Division Simulations show ring oscillator works around 2GHz, we select 1/64 of 2GHz to be the reference, and simulate to prove functionality. 37 Stage Ring Oscillator

  15. Transient Simulation with Reference = 61.7 MHz

  16. Power Consumption The ring oscillator consumes the most power because it is constantly switching. The current to the ring oscillator was on the order of 0.4mA so the power is about 0.4mW. The charge pump consumed the second most amount of power. When the ring oscillator starts locking to reference signal, it consumes lots of power because of DC current flowing. As the signal is locked, charge pump will mainly off and it will not consume lots of power. The PFD and frequency divider consumed the least amount of power (~0.05mW).

  17. Errors and Future Work Locking time grows significantly when the size of ring oscillator and feedback loop is growing. Need longer simulation time Implement 1/N Frequency Divider where N is not 2^n

  18. Reference [1] http://www.cse.unt.edu/~smohanty/Projects/DUE_0942629/Fall2011_ATV07_PLL-Design.pdf - Overview of Phase Locked Loops from a VLSI Perspective [2] http://dspace.mit.edu/bitstream/handle/1721.1/33386/62559899-MIT.pdf?sequence=2 - PhD Thesis on Phase Locked Ring Oscillator for Wireless Applications [3] http://www.ijsce.org/attachments/File/v2i2/B0529042212.pdf - Paper on Phase Frequency Detector and Charge Pump Design

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