The Proposed On-Chip Bus System with GALDS Topology

1. The Proposed On-Chip Bus System with GALDS Topology National Sun Yat-sen University Embedded System Laboratory Presenter :Ching-Hua Huang Chang-Won Choi ; Jae-Kyung Wee ; Gyu-Sung Yeon ; Electron. Eng., Soongsil Univ., Seoul 2008 InternationalSoC Design Conference

2. Abstract The novel low power multitasking bus based on globally asynchronous, locally synchronous system with dynamic voltage and frequency scaling (GALDS) is proposed for System on-Chips. Our proposed key blocks consists of three distinct components: a novel wrapper-based and bidirectional segmented bus, a newly proposed asynchronous wrapper having bidirectional low-latency FIFOs to communicate between independently clocked synchronous IPs, and a clock distribution system having multiple times of the basic bus clock(fBUS)tobesupported for all wrappers and IPs. In addition to being capable of reducing power consumption on multitasking operations, the proposed GALDS has structural merits of the easy scalability and modularity by increasing the bus segments and modifying bit controls, and has a relatively low latency compared with other asynchronous bus systems due to IP communications with multiple times of a basic bus clock. Also, the proposed bus can be supported for ARM-based SOC platform with a wrapper satisfying protocols of AMBA™ AHB between the bus and local IPs. With testing the implementation of the proposed bus, we obtain the robust operations through all dynamically frequency-changed multitasking read and write communications between four master IPs and four slave IPs.

3. What’s the problem 3 • IT products • Multitasking operation , High performance • Low power , Low area • Increase the digital circuit’s complexity • In such SoC designs • Multiple masters and slaves • Multiple clock domains • Multiple power domains

4. Related work [10] Clock Distribution Be used based on multiple times of fBUS to be supported for all wrappers and IPs. [9] Asynchronous Wrapper [7] Power Mangement Unit [4,5] Segmented Bus Can be VCI and OCP to reuse IPs easily A pipelined architecture to support multitasking on a single layer bus. The PMUis in control of supplying voltage and frequency with each IP [This paper] GALDS 4

5. Proposed Methods • Globally Asynchronous , Locally synchronous system with Dynamic voltage and frequency Scaling (GALDS) Power Mangement Unit Asynchronous Wrapper Segmented Bus

6. Segmented bus rate of simultaneous transaction=100% rate of simultaneous transaction=50%~75% rate of simultaneous transaction=25%

7. Asynchronous Wrapper

8. Asynchronous FIFO Full/Empty happen Handle different clock Read pointer Write pointer

9. Modified Asynchronous FIFO Because IP frequency changes with multiple times of a basic bus clock. Thus, Asynchronous wrapper uses the Modified Asynchronous FIFO.

10. The Latency of Asynchronous FIFOs (16-Busrt Mode)-Master Wrapper Master IP FIFO IN Master Wrapper FIFO OUT Segmemted Bus ND is the number of data. S(0 ≤ S ≤1) is the rate of single mode transfer. B is the size of the burst data.

11. The Latency of Asynchronous FIFOs (16-Busrt Mode)-Slave Wrapper Segmemted Bus FIFO IN Slave Wrapper FIFO OUT Slave IP

12. Simulation results (NM=4, B=16, ND=1000, S=0.2) fREAD: fWRITE NM : number of master B : 16-burst data ND : number of data S: single transfer ratio When Rmultiple_trans is more than 40%, the GALDS bus is better latency performance than pipelined transaction of AMBA AHB. Comparison of the latencies according to data transfer type and the rate of simultaneous transaction 12

13. Simulationresults(cont.) (Rmultiple_trans=0.6, B=16, ND=1000,S=0.2) Rmultiple_trans : rate of simultaneous transaction B : 16-burst data ND : number of data S : single transfer ratio GALDS bus is better latency than AMBA AHB, when the number of master is more than three. Comparison of the latencies according to the number of master IP

14. Conclusions • Accurate communication between differential clock domains is possible • Improved in data bandwidth to complicated SoC • Able to change operation frequency and voltage • According to the bus usage of IPs to the PMU, so it can reduce power consumption of the total system. • Be expected to play an important part in SoC design • High performance , Low power consumption and Multi-clock.

15. My comments • Learn the related concept of multi-clock. • GALDS bus system • Segmented bus • Asynchronous wrapper • Asynchronous FIFO • This paper has some typo and the statements are ambiguous. • Word (like GADLSGALDS) and Block (Asynchronous Wrapper) • Block concept and design flow