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Modeling 32 V Asymmetric LDMOS Using Aurora and Hspice Level 66

Modeling 32 V Asymmetric LDMOS Using Aurora and Hspice Level 66 . By Alhan Farhanah, Mohd Shahrul Amran, Albert Victor Kordesch Device Modeling Department, SILTERRA Malaysia Sdn. Bhd. 2007. Outline. Aurora and HSPICE Level 66 Background 32V Asymmetric HV MOS Background

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Modeling 32 V Asymmetric LDMOS Using Aurora and Hspice Level 66

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  1. Modeling 32 V Asymmetric LDMOS Using Aurora and Hspice Level 66 By Alhan Farhanah, Mohd Shahrul Amran, Albert Victor Kordesch Device Modeling Department, SILTERRA Malaysia Sdn. Bhd. 2007

  2. Outline • Aurora and HSPICE Level 66 Background • 32V Asymmetric HV MOS Background • Modeling Flow for Asymmetric HV MOS • Results and Discussion • Self Heating Effect in HV MOS • Conclusion ESSDERC 2007 MUNICH

  3. Aurora and HSPICE Level 66 Background • Aurora • product of Synopsys Inc for Modeling. • Beside HSPICE Level 66, Aurora also offers all types of models that normally offered by other products. • Contends for the modeling and SPICE simulation of digital CMOS, analog and RF circuit that operates up to 100V. ESSDERC 2007 MUNICH

  4. Aurora and HSPICE Level 66 Background (cont’d) • HSPICE Level 66 is a proprietary product of Synopsys. • HSPICE Level 66 model • self heating, forward and reverse mode, asymmetric parasitic, and bias dependent RDS- based on BSIM4 • primarily targets for LDMOS (Lateral Double Diffused MOSFET) and EDMOS (Extended Drain MOSFET) device technologies. ESSDERC 2007 MUNICH

  5. 32V Asymmetric HV MOS Background (cont’d) Structure ESSDERC 2007 MUNICH

  6. Golden Die Asymmetric Behavior Checking DC Measurement AC Measurement Aurora Extraction And Optimization Hspice Simulation Modeling Flow For Asymmetric HV MOS ESSDERC 2007 MUNICH

  7. Modeling Flow For Asymmetric HV MOS(cont’d)Asymmetric Behavior Checking • Purpose - check the asymmetric effect of the transistor. • Measurement - swapping the bias voltage of source and drain for each measurement. • Compare IdVd curve for forward and reverse mode measurement. ESSDERC 2007 MUNICH

  8. Modeling Flow For Asymmetric HV MOS (cont’d)Asymmetric Behavior Checking Almost similar ID Long Channel Device (W/L=25u/25u) +++ forward mode ___ reverse mode ESSDERC 2007 MUNICH

  9. Significant ID decrease Asymmetric Behavior Checking VGS +++ forward mode ___ reverse mode Short Channel Device (W/L=25u/4.25u) ESSDERC 2007 MUNICH

  10. Modeling Flow For Asymmetric HV MOS (cont’d) • The results showed that shorter length device exhibits quite significant Id decrease for reverse mode measurement while the long channel device exhibits almost similar Id curve for both modes of measurement ESSDERC 2007 MUNICH

  11. Modeling Flow For Asymmetric HV MOS (cont’d) DC Measurement • Measurements: • IdVg@low Vdd with different Vb • IdVg@high Vdd with different Vb • IdVd @Vb=0 with different Vg • IdVd @high Vb with different Vg • Before measuring all the modeling devices, Wide Width and small Length transistor with different back biases and different temperatures must be evaluated first ESSDERC 2007 MUNICH

  12. Modeling Flow For Asymmetric HV MOS (cont’d) CV Measurement • To properly model the effect of asymmetric, the modeling structure for CV need to be designed with extra structures compare to symmetric structure. • All the CV modeling structures need to be separated into 2 different structures: • Source design rule • Drain design rule. • Thus, the CV measurement for asymmetric transistor is almost double compare to symmetric transistor. ESSDERC 2007 MUNICH

  13. Modeling Flow For Asymmetric HV MOS (cont’d) Extraction and Optimization • Extraction strategy – almost similar to BSIM4 • The preferred mobility model in Level 66 • MOBMOD=0 • Source and Drain parameters are not equal. e.g RSW and RDW, RSWMIN and RDWMIN • Both drain side and source side bias dependence parameters of LDD resistance can be optimized. ESSDERC 2007 MUNICH

  14. Modeling Flow For Asymmetric HV MOS (cont’d) Extraction and Optimization • There are reverse mode parameters available for optimization i.e ETA0I, ETABI, DSUBI • Too many of these parameters are not encouraged. • Self heating effect can be turned on by setting SHMOD=1 and RTH0>0. • Strongly advised to set TSHFLAG=1 during the optimization - internal approximation of self heating effect will be used during the optimization. Hence, the speed of the optimization is significantly improved. In the final step, the optimization can be refined by setting TSHFLAG=0. • When self heating is turned on, the temperature parameters need to be extracted as much as possible before we do extraction for saturation region parameters. ESSDERC 2007 MUNICH

  15. Modeling Flow For Asymmetric HV MOS (cont’d) Extraction and Optimization • Disadvantages of Level 66 model: • Slower model evaluation -includes internal nodes (solver need to be invoked for every bias point) • There is no reliable way to extract thermal capacitance. Thus, we need to develop a method to include thermal time constant in our model. ESSDERC 2007 MUNICH

  16. Results and Discussion W/L = 25um/25um +++ Meas ___ Model ESSDERC 2007 MUNICH

  17. Results and Discussion(cont’d) W/L = 25um/4.25um +++ Meas ___ Model ESSDERC 2007 MUNICH

  18. Results and Discussion(cont’d) W/L = 25um/25um +++ Meas ___ Model ESSDERC 2007 MUNICH

  19. Results and Discussion (cont’d) W/L = 25um/4.25um +++ Meas ___ Model ESSDERC 2007 MUNICH

  20. Results and Discussion (cont’d) Idsat (uA/um) ESSDERC 2007 MUNICH

  21. Results and Discussion (cont’d) Vth (V) ESSDERC 2007 MUNICH

  22. Results and Discussion(cont’d) +++ Meas ___ Model ESSDERC 2007 MUNICH

  23. Results and Discussion(cont’d) +++ Meas ___ Model ESSDERC 2007 MUNICH

  24. Results and Discussion (cont’d) • In this paper, IdVg and IdVd curves for 25um/25um and 25um/4.25um have been used to demonstrate model accuracy. • The model also correctly simulates self heating effect • The model scalability (across W and L) also showed a good agreement with measurement data. Less than 5%. • The accuracy of the AC behavior is excellent. Less than 1%. ESSDERC 2007 MUNICH

  25. Self Heating Effect in HV MOSFET Gate Source Drain POLY HPWELL STI P+ STI N-DRIFT N+ N-DRIFT N+ STI HEAT P-Sub • If P is moderate(mW), self heating is not severe since it reach its thermal equilibrium with its environment ESSDERC 2007 MUNICH

  26. Self Heating Effect in HV MOSFET (cont’d) Experimental setup VDD 4.7F 50 VD VG Pulse Gen oscilloscope ESSDERC 2007 MUNICH

  27. Self Heating Effect in HV MOSFET (cont’d) VG VD Dynamic response of HV NMOS to typical gate pulse ESSDERC 2007 MUNICH

  28. Self Heating Effect in HV MOSFET (cont’d)RTH extraction • RTH will be extracted from Aurora by fitting the data for W=25um and different L. • set SHMOD=1 and RTH0>0. • This is to ensure that the RTH can be scaled with L. ESSDERC 2007 MUNICH

  29. Transient drain-current characteristics of HV NMOS Due to SHE ESSDERC 2007 MUNICH

  30. Time constant for self heating of HV NMOS ESSDERC 2007 MUNICH

  31. Self Heating Effect in HV MOSFET (cont’d)Extracted time constant and CTH • Time constant is extracted from : y = 2.3011e-0.0546x where thermal time constant, RTH CTH = 1/0.0546 = 18.32 us From Aurora extraction RTH = 6.85E-03 mºC/W Hence the extracted thermal capacitance: CTH = 18.32us/RTH = 2.67E-03 (W*sec)/ mºC ESSDERC 2007 MUNICH

  32. Conclusion • Modeling strategies for 32V asymmetric HV MOSFET using Aurora and HSPICE level 66 has been presented • Model shows: • Excellent DC IV results for entire DC bias range • Excellent behavior of junction capacitances • Model scalability (across W and L) also showed good agreement with measurement data. Less than 5% • Correctly simulate SHE • Extraction of Thermal resistance and capacitance by Pulsed gate measurement ESSDERC 2007 MUNICH

  33. Thank You ESSDERC 2007 MUNICH

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