CSS 372 Oct 4th - Lecture 3

1. CSS 372 Oct 4th - Lecture 3 Chapter 3 – Connecting Computer Components with Buses Bus Structures Synchronous, Asynchronous Typical Bus Signals Two level, Tri-state, Wired Or Hierarchical Bus Organizations PCI Bus Example

2. Types of Buses • Synchronous • Asynchronous (Hand Shaking) • Serial (Twisted pair, Coaxial Cable, ..) • Parallel (Ribbon Cable,

3. Types of Buses • Dedicated • Separate data & address lines • Multiplexed • Shared lines • Address valid or data valid control line • Advantage - fewer lines • Disadvantages • More complex control • Ultimate performance

4. Physical Considerations for Buses • Media (voltage, optic) • Signal levels – the higher, the more immune to noise • Noise Absorption – wires can pick up noise from neighboring wires • Noise Generation – wires can be antennas • Length Creates Delay ( reduces Bandwidth) Consumes Power Creates reflections – (Terminations become more critical)

5. Logic Threshold Voltage Levels

6. Signal Scheme Alternatives • Totempole - High or Low output level Line always at a 1 level or 0 level • Open collector, open drain, wired-or Line is nominally at a 1 level or 0 level – line is “pulled” to non-nominal level • Tristate Has third state – open • Differential Uses a pair of lines – the level is the difference of signals on the two lines.

7. Bus Challenges • Lots of devices on one bus leads to: • Propagation delays • Long data paths mean that co-ordination of bus use can adversely affect performance • Traffic congestion • Too many devices communicating reduces bandwidth • Alternative - Systems use multiple buses

8. Simple Computer Bus + clock(s), power(s), and ground(S) Notes: 1) Bus lines need to be properly terminated 2) Power lines are to furnish reference voltage, not power

9. Adding an Expansion Bus

10. Hierarchical Bus Structure

11. Bus Arbitration • More than one module may need to control the bus e.g. CPUs and DMA controller • Only one module may control the bus at one time • Arbitration may be centralised or distributed

12. Centralised or Distributed Arbitration • Centralised • Single hardware device controlling bus access • Bus Controller • Arbiter • May be part of CPU or separate • Distributed • More than one module may claim the bus Need control logic on all these modules

13. Timing • Co-ordination of events on bus • Synchronous • Events determined by clock cycles • Control Bus includes clock line(s) • A single 1-0 is a bus cycle (or phase) • All devices can read clock line • Usually sync on leading edge • Usually a single cycle for an event (may be multiple clock cycle)

14. Timing Diagram Conventions

15. Synchronous Timing Diagram

16. Asynchronous Timing – Read Diagram

17. Asynchronous Timing – Write Diagram

18. Example - PCI Bus • Peripheral Component Interconnection • Intel released to public domain • 32 or 64 bit • 50 lines

19. Typical PCI Bus Usage

20. Multiple PCI Bus Configuration

23. PCI Commands • Transaction between initiator (master) and target • Master claims bus • Determine type of transaction • e.g. I/O read/write • Address phase • One or more data phases

24. PCI Read Timing Diagram

25. PCI Bus Arbiter

26. PCI Bus Arbitration Timing