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ANA: A Flexible and High-Performance Network Architecture?

Ariane Keller Bernhard Plattner. ANA: A Flexible and High-Performance Network Architecture? . Research Questions. Application. System Architecture Alternatives. Novel Architecture. Internet Architecture. Application. Prediction. Routing. Transport. Network. Security. Monitoring.

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ANA: A Flexible and High-Performance Network Architecture?

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  1. Ariane Keller Bernhard Plattner ANA:A Flexible and High-Performance Network Architecture? Research Questions

  2. ariane.keller@tik.ee.ethz.ch Application System Architecture Alternatives Novel Architecture Internet Architecture Application Prediction Routing Transport Network Security Monitoring Link Link Transport System designed to supportexactly this protocol stack System designed to supportany protocol stack DYNAMIC BINDINGOptimized for flexibility STATIC BINDINGOptimized for performance

  3. ariane.keller@tik.ee.ethz.ch System Requirements • Different protocol stacks at the same time • Change protocol stack when needed (at runtime) • Insert monitoring functionality • Add encryption • Add new “protocol layer” • Achieve “high” performance

  4. ariane.keller@tik.ee.ethz.ch Envisioned Hardware Setup PCI Bus NIC FPGA(Virtex2/4/5) CPU EthPort(s) • Execution of performance critical functions in hardware • Partially reconfigurable FPGA • Execution of non-critical functions in software • CPU of host system • NIC: • NetFPGA • RiceNIC (with Avnet Board) • Combocard(from Liberouter)‏

  5. ariane.keller@tik.ee.ethz.ch How is High-Performance Defined? • Depends on actual network traffic • FTP traffic: High throughput • Voice traffic: Low latency • Characterization of network traffic • Online profiling of network traffic • Count the number of packets each functional block processes • Provide meta-data about optimization goals of the block

  6. ariane.keller@tik.ee.ethz.ch Performance Optimization • Determine which functional block is implemented in hardware and which in software • Based on node local information only • Number of packets processed by each functional block • Meta data provided by each individual functional block • Optimization goals provided by applications • Additional information received from other nodes • “Flood” optimization goals through network

  7. ariane.keller@tik.ee.ethz.ch My (Potential) Research Questions • Is it possible to make use of FPGAs to build a flexible network architecture, such as ANA? • What is the impact of flexibility on performance? • How can we characterize “good performance” for a given network traffic? • Can we optimize the performance according to the characterization of the current network traffic?

  8. ariane.keller@tik.ee.ethz.ch Related Work: Online Profiling • A reconfigurable platform for multi-service edge routers • Christoforos Kachris, Stamatis Vassiliadis (Delft University of Technology) • Goal: lower power consumption by requiring less hardware • 3 flow types (ip-forward, encryption, compression) • Count processed packets for each flow type • Number of processing units (HW only) adjusted based on ratio between flow types • A reconfigurable platform for multi-service edge routers (SBCCI 2007)

  9. ariane.keller@tik.ee.ethz.ch Related Work: Online Partitioning • ReCoNet • Thilo Streichert, Dirk Koch, Jürgen Teich, (Erlangen-Nuremberg) • Goal: Tolerate link as well as node defects in self-adaptive reconfigurable networks • Migration of tasks between HW/SW and between different nodes • Criteria: • Communication overhead • Task migration overhead • Implementation according to favorite implementation style • Equally balance load between SW and HW • Dynamic Task Binding for HW/SW Reconfig. Networks (SBCCI 06)

  10. ariane.keller@tik.ee.ethz.ch Related Work: Online Profiling and Reconfiguration • DynaCore • Carsten Albrecht, Thilo Pionteck, Erik Maehle (Lübeck) • Goal: Improve flexibility, adaptability and performance of network processors by means of a dynamically reconfigurable coprocessor. • Computation intensive tasks offloaded to dynamically reconfigurable FGPA. • Use of „monitors“ to deside which functionality is implemented on the FPGA • DynaCore: Dynamically adaptable Coprocessor based on Reconfiguration (PDP 2006)

  11. ariane.keller@tik.ee.ethz.ch Open Questions: Relevant Literature • Runntime HW/SW partitioning that adapt „autonomously“ to changing environments • HW/SW Codesign for packet processing systems • Modelling of networking tasks(not start-, executiontime, deadline) • Implementations that use dynamically reprogrammable FPGAs.

  12. ariane.keller@tik.ee.ethz.ch People I’d like to talk with • John Lockwood • FPX, NetFPGA • Someone from ReCoNets • Herbert Walder or Marco Platzner • Operating System for dynamically reconfigurable FPGAs. • Someone from DynaCore

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