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San Jose State University Electrical Engineering

San Jose State University Electrical Engineering. EE-166 4 Bit Serial to Parallel Converter Prof. David Parent, PhD Members: Quang Ly Derek Kwong Hector Vidal. San Jose State University Electrical Engineering. Specifications: Clock f = 25 MHz, duty cycle = 50%

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San Jose State University Electrical Engineering

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  1. San Jose State UniversityElectrical Engineering EE-166 4 Bit Serial to Parallel Converter Prof. David Parent, PhD Members: Quang Ly Derek Kwong Hector Vidal

  2. San Jose State UniversityElectrical Engineering Specifications: • Clock f = 25 MHz, duty cycle = 50% • Conversion every 4 clock cycles • Output Cload = 10 pF • Power < 500 mW

  3. San Jose State UniversityElectrical Engineering Block Diagram:

  4. San Jose State University Electrical EngineeringD Flip-Flop with Reset Schematic:

  5. San Jose State University Electrical EngineeringCounter Schematic:

  6. San Jose State University Electrical EngineeringSerial to Parallel Schematic:

  7. San Jose State University Electrical EngineeringOutput Buffer Schematic:

  8. San Jose State University Electrical Engineering4bit Serial to Parallel Test Bench Schematic:

  9. San Jose State University Electrical EngineeringSimulation waveforms:

  10. San Jose State University Electrical EngineeringSimulation waveforms:

  11. San Jose State University Electrical EngineeringSimulation waveforms (Reset):

  12. San Jose State University Electrical Engineering Super Buffer Design: • Stage 1: Wp=250.4 mm, Wn= 90 mm • Stage 2: Wp= 89.2 mm, Wn= 32 mm • Stage 3: Wp= 32 mm, Wn= 11.6 mm • Stage 4: Wp= 11.6 mm, Wn= 4 mm • a= 2.88

  13. San Jose State University Electrical Engineering4bit Serial to Parallel Circuit Layout:

  14. San Jose State University Electrical Engineering Counter Layout:

  15. San Jose State University Electrical Engineering D Flip-Flop Layout:

  16. San Jose State University Electrical Engineering Output Buffer Layout:

  17. San Jose State University Electrical Engineering Serial to Parallel Layout:

  18. San Jose State University Electrical EngineeringFinal Product:

  19. San Jose State University Electrical Engineering Super Buffer Layout:

  20. San Jose State UniversityElectrical Engineering Test results: • Rise time (tr) = 3.9 ns • Fall time (tf) = 4.05 ns • Total area = 22.5 mil2 • Power < 350 mW • Peak current = 16.6 mA

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