Synplicity Tutorial for CSE 535

1. Synplicity Tutorial for CSE 535 • Michael Attig (mea1@arl.wustl.edu)

2. What is it? • Synplicity compiles your vhdl source code and creates an edn/edf file • An edn/edf file: • Creates a netlist (a generic language describing what the circuit will do) • Optimizes blocks/logic Source: pg 3 of http://www.synplicity.com/literature/pdf/prod_overvw03_final.pdf

3. How will we use it? • We will use Synplicity to create an edn file of snort_app • You will submit this edn file to be: • Used in Xilinx’s Ngdbuild

4. Step 1 • Open Synplify Pro • In the File menu, select ‘New Project’ • You should see the following screen

5. Step 2 • Click the ‘Impl Options’ Button on the left side • In the Device Tab set the following: • Technology: Xilinx Virtex-E • Part: XCV2000E • Speed: -6 • Package: FG680 • Under Device Mapping Options: • Check Disable I/O Insertion

6. Step 3 • In the Constraints Tab • Set Frequency to be 25 MHz

7. Step 4 • In the Implementation Results Tab: • Set the Results directory to be your ‘syn’ directory • Set the Result File Name to be snort_app.edn • Select ‘Write Mapped VHDL Netlist’ • Select ‘Write Vendor Constraint File’ • Click OK

8. Step 5 • Click Add File • Add all files • Arrange your files in hierarchical order (i.e your top level file, snort_app, should be listed last)

9. We’re Ready! • Everything is set up now. You can click the big ‘RUN’ button at the top. • This will compile and map your design. • Warnings and Errors will be reported to you in the lower left window. • A .edn file will appear in your syn directory.