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SFI-4.1

SFI-4.1. Brian Von Herzen, Ph.D. Xilinx Consultant, www.FPGA.com. OIF Electrical Interfaces. What are the OIF Electrical Interfaces? SPI-5 SFI-5 SPI-4.2 SPI-4.1 SFI-4 SPI-3. SFI-4.

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SFI-4.1

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  1. SFI-4.1 Brian Von Herzen, Ph.D. Xilinx Consultant, www.FPGA.com

  2. OIF Electrical Interfaces • What are the OIF Electrical Interfaces? • SPI-5 • SFI-5 • SPI-4.2 • SPI-4.1 • SFI-4 • SPI-3

  3. SFI-4 • SFI-4 (OC-192 SERDES-Framer Interface) OIF-PLL-02.0 Proposal for a common electrical interface between SONET framer and serializer/deserializer parts for OC-192 interfaces)

  4. System Packet Interface Level 5 (SPI-5): OC-768 System Interface forPhysical and Link Layer Devices • SPI-5 connects Physical to Link Layer Devices • Fabric interface chips (FIC) • Traffic managers • Network processing element (NPE’s)

  5. SPI-5 Signals • The SPI-5 interface uses clock forwarding between • PHY • Link Layer Devices • Up to 3.125 Gbps • 16 lanes • 50 gigabits per sec • OC-768 with 25% overspeed

  6. SFI-5 • SERDES Framer Interface Level 5 (SFI-5): Implementation Agreement for 40Gb/s • Interface for Physical Layer Devices

  7. SPI-4.2 • System Packet Interface Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Layer Devices

  8. SPI-4.2Interface for Physical and Link Layer Devices • Uses 16 lanes at 622 Mbps or faster

  9. SPI-4.1 • System Physical Interface Level 4 (SPI-4) Phase 1: • A System Interface for Interconnection Between: • Physical and Link Layer, • Peer-to-Peer Entities Operating at 10 Gbps (OC-192). • 64 Data Signals at • 200 MHz

  10. SPI-3 • System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link Layer Devices

  11. OIF Electrical Standards Benefits • Enables “Best-In-Class” selection of devices that interoperate • SERDES • FEC • Framers • Traffic Management • Fabric Interfaces • System vendors can choose their favorite feature sets and mix and match components as needed

  12. OIF Electrical Standards Benefits (continued) • With interoperable standards, vendors can • Mix and Match “best of breed” components • Minimize the engineering to connect components • Reduce time to market • Enable customization using programmable logic for key components

  13. System Design Example • A systems vendor wanting to build an OC-768 switch with OIF standards can select: • A customized traffic manager from FPGA Vendor X • A framer from ASSP vendor Y • A SERDES module from Optical Vendor Z FPGA Vendor X Optical Vendor Z ASSP Vendor Y

  14. OIF Electrical Standards Silicon Solutions • A variety of Silicon implementation solutions are available, including: • ASSP + FPGA • ASIC • System vendors do not get locked in to a proprietary solution • OIF-compliant chips interoperate effectively to enable “best of breed” system solutions

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