B5: Designing for Signal and Power Integrity in FPGA Designs

1. B5: Designing for Signal and Power Integrity in FPGA Designs Mark Alexander 9/10/2002

2. Agenda • Motivation: Vulnerabilities of high-speed FPGAs • Signal Integrity Concerns • Transmission Lines • Termination • I-Grade Parts • Power Integrity Concerns • Keeping it Clean • Conclusion

3. Motivation • Digital device speeds have increased – quickly! • Signal transition times have passed a critical point • Everything is a Transmission-line • Device density has passed a critical point • Transient current demands are now wideband • New design methods are needed • Otherwise, everything fails and we don’t know why

4. It’s time to relearn that analog stuff you hated so much for so long!!

5. SI/PI: Signal and Power Integrity • Signal Integrity Engineering • Signal waveforms of Data and Clock • Signal transition time is the most important factor • Dependent on device speed – not clock frequency! • Proper PCB Design is the most critical factor • Power Integrity Engineering • How to build a good PDS (power distribution system) • Must accommodate wideband transient currents • Proper PCB Design is the most critical factor

6. Signal Integrity • Transition time (rise/fall time) • Has gone from 10ns to 1ns in the past ten years • For 40cm board • 10ns rise time requires no thought – pure digital • 1ns rise time has big implications • Every PCB trace is a transmission line • Any impedance discontinuity can cause reflection • Reflections cause: • Overshoot • Ringing • Bad data • EMI • Need for impedance CONTINUITY

7. Impedance Continuity • Requires • Controlled impedance PCB traces • Must be specified by the PCB Designer • Reference planes must be present in PCB stackup • Knowledge of all impedances in the channel • driver Z, trace Z, receiver Z • Impedance modifications, in most cases • That’s what termination is for!

8. Termination • Can be resistors, capacitors or diodes • Resistors are easiest to use • For details, see Johnson and Graham book (Appendix I) • Usually discrete external resistors • On-chip termination is now available! • Altera and Xilinx both offer this feature • Crude on-chip series-termination is available in all PLDs • Just select a lower-strength driver – 6mA, 8mA etc.

9. Importance of Simulation • Simulation is the only way to analyze T-line behavior • IBIS and SPICE are the two main methods • SPICE is accurate, but difficult and time consuming • IBIS is adequate, fast, and it’s easy to get models • IBIS runs out of steam at 500 MHz • SPICE should be used for multi-gigabit serial designs • Allows easy “what-if” analysis • Always simulate all process and environment corners • Best P, High V, Low T = fast device  signal integrity verification • Worst P, Low V, High T = slow device  timing verification

10. Impact of Industrial Designation • High-rel and hostile environment applications often use I-grade parts • I-grade has wider temperature range than C-grade parts • Commercial grade: 0°C to 85°C junction temperature • Industrial grade: -40°C to 100°C junction temperature • I-grade parts have faster silicon to accommodate higher temperatures and • I-grade parts are often used at lower temperatures therefore • Edge rates for I-grade parts are even faster than for typical FPGAs! Simulate all corners! More signal integrity problems

11. People forget this one! Power Integrity • Power Distribution System (PDS) is central point • Purposes of PDS: • Deliver power • Maintain low noise! • Basic parts of PDS: • Voltage source (Vreg or Power Supply Circuit) • Power planes in PCB stackup • Decoupling capacitors

12. leads to What if there is noise? Excessive noise on the power supplies Jitter on all signals Noise on Vcco  timing jitter on I/O signals Noise on Vccint  timing jitter on core signals Noise on Vccaux  timing jitter on clock resources

13. Where’s the problem? • Power supply noise DOES NOT come from the Vreg • Noise comes from the devices themselves • Digital circuits are noisy! • Source of all PDS noise: • Transient currents flowing through parasitic inductances • Where do transient currents come from? • Large portions of device enabled/disabled (seconds, days) • Clock events – all flops change state at once (nanoseconds) • Harmonics of square waves (picoseconds) • All these things together make wideband noise

14. Wideband solution • FPGA needs easy access to extra current • Bypass capacitors and planes provide this • But they have drawbacks • They have parasitics of their own • Each one only works over a narrow frequency range • Solutions to these drawbacks • Use many caps in parallel to reduce parasitic effects • Use many cap values to cover wide frequency range 470uF, 47uF, 2.2uF, 0.1uF, 0.01uF, 0.001uF

15. PDS Design for FPGAs • One capacitor per Vcc pin • Yes, EVERY Vcc pin – Vccint, Vcco, Vccaux, Vref • Within the total count for each supply: • Allocate some in each frequency range • 1% 470 uF • 3% 47 uF • 6% 2.2 uF • 15% 0.1 uF • 25% 0.01 uF • 50% 0.001 uF • Power planes and/or sandwiches are a must

16. Then Simulate • Simulation is needed to view network impedance profile • Should cover frequencies from 500 kHz to 800 MHz • Impedance should be low and flat over this range

17. Must have 1 GHz or better scope Must have 1 GHz or better probes Probe power vias on back of board Use infinite persistence mode Then Build and Measure • Noise on all supplies should be less than 10% of nominal • Measure with a fast oscilloscope

18. READ XAPP623 • Many important details have been left out here • System engineers MUST be familiar with • System vulnerabilities • Common pitfalls • Proper design techniques and methods • Also consult other PDS references: • SI Central • Online design communities • Get trained!

19. Conclusion • FPGA system design is not just VHDL and Verilog • Faster devices mean new challenges • Everything is a transmission line • Signal Simulation is vital • Good PDS Engineering is essential • Use lots of capacitors • Get trained, stay current, and read the fine print!

20. Appendix IREFERENCES • Howard Johnson and Martin Graham, High Speed Digital Design: A Handbook of Black Magic, Prentice Hall, New Jersey, 1993. • Mark Alexander, XAPP623 PDS Design: Using Bypass/Decoupling Capacitors, Xilinx Appnote, 2002. http://www.xilinx.com/xapp/xapp623.pdf

21. Appendix IIUSEFUL RESOURCES • Signal Integrity Central – Xilinx site with links to all Xilinx SI literature http://www.xilinx.com/signalintegrity • PCB Checklist – Checklist with all pertinent items and explanations, links http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=si_pcbcheck • SI Reflector – Good discussion list with its share of gurus Si-list-request@freelists.org, archives athttp://www.freelists.org/archives/si-list • Your local EMC Society – Excellent resource to help you stay current http://www.ewh.ieee.org/soc/emcs • SI Training from qualified experts – Fast path to success http://www.gigatest.com Eric Bogatin http://www.signalintegrity.com Howard Johnson http://www.speedingedge.com Lee Ritchey http://www.ultracad.com Doug Brooks

22. Appendix III:BASIC DECOUPLING RULES • Use small capacitor packages • Parasitic L is proportional to pkg. size • Use largest value in a given package • L is dominated by pkg, so maximize C • Connect cap lands directly to planes • NEVER share cap vias • Keep trace between land and via short!! • Benefit of small package is lost otherwise