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Two Dimensional Highly Associative Level-Two Cache Design

Two Dimensional Highly Associative Level-Two Cache Design. Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Mar-26. Outline. Information of literature Background Introduction of CAM

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Two Dimensional Highly Associative Level-Two Cache Design

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  1. Two Dimensional Highly Associative Level-Two Cache Design Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Mar-26

  2. Outline • Information of literature • Background • Introduction of CAM • Previous Research • 2D-Cache Organization • 2D-Cache Operation • Comparison

  3. Information of literature Two Dimensional Highly Associative Level-Two Cache Design Chuanjun Zhang and Bing Xue IEEE International Conference on Computer Design, 2008. (ICCD 2008)

  4. Background • Highly associativity is important for L2 Cache • Highly associative caches increase HW cost • More comparator • More routing wires • Tag stored in CAM cells facilitate tag comparison • CAM cells are power costly and consume large area • LRU replacement is only implemented in low associative caches. • Random replacement needs simple HW, but has higher miss rate than LRU

  5. Introduction of CAM CAM: Content Addressable Memory

  6. Previous Research • CAM based method for low associative caches are conducted in such aspects, • Low HW complexity • Low miss rate • Low miss penalty • SW controlled fully associative has better flexibility This work focuses on inexpensive highly associative L2 cache

  7. 2D-Cache Organization For Column For Row

  8. 2D-Cache Operation (1/2) • Search for the hit block for a cache hit • All the column are searched concurrently • Search for the victim block for a cache miss • No CAM tag matches the desired address • Each column has one CAM tag matches the desired address • Some columns have CAM tag hits while remaining columns do not have CAM tag hits 2D-Cache layout

  9. 2D-Cache Operation (2/2) LRU in column Random in Row

  10. Benchmark Results (1/3) 26 SPEC2K CAM-bit v.s. Miss rate

  11. Benchmark Results (2/3) Ways in row v.s. Miss rate (ways in column is constant to 8)

  12. Benchmark Results (3/3) Replacement Policy v.s. Miss rate (Row-Column)

  13. Comparison (1/3) Energy and Latency of diff. caches

  14. Comparison (2/3) IPC reduction over the 8-way caches

  15. Comparison (3/3) Energy reduction over the 8-way caches

  16. Question Thanks!

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