1 / 7

Schedule and resources

Schedule and resources. SPIDER has been streamlined to cover: 1) 1 submission ‘small pixel’ ISIS (vertexing/tracking - LCFI ) test chip 2) 1 optimised CMOS pixel detector optimised for vertexing/tracking 3) 1 submission large TPAC ( CALICE ) test chip

abedi
Download Presentation

Schedule and resources

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Schedule and resources • SPIDER has been streamlined to cover: • 1) 1 submission ‘small pixel’ ISIS (vertexing/tracking - LCFI) test chip • 2) 1 optimised CMOS pixel detector optimised for vertexing/tracking • 3) 1 submission large TPAC (CALICE) test chip • Note – This will be investigated for use by FAIR (Nuclear Structure) • 4) Calorimeter stack • Costs have been reviewed and reduced by (sequentially) • 1)Minimising submissions • 2)Reducing the infrastructure requirements • 3)…and finally making cuts on groups (to be agreed) • Bottom-up check starting from TPAC, DCAL, ISIS, 4TDP25 • Schedule optimisation consists of adjusting timing to take account of: • 1) An early start needed by TPAC to be able to complete the full stack test • 2) Smooth out the design and testload M. Tyndel, SPIDER proposal 1 Jul 30th , phone

  2. Schedule and resources • Thanks to Renato (he is prepared to support us making an early start) there are 2 options to consider: • 4TDP25 (Jessica) late • Peaked design and test workload • 4TDP25 is on critical path • Exposes 4TDP25 and/or the DCAL stack to risk of being cut • 4TDP25 (Jessica) early • Requires more design effort early in the program • Provides less risk to tracking/vertexing part • Exposes DCAL stack to risk of being cut M. Tyndel, SPIDER proposal 2 Jul 30th , phone

  3. Option-i (4TDP25 late) M. Tyndel, SPIDER proposal 3 Jul 30th , phone

  4. Option-ii (4TDP25 early) M. Tyndel, SPIDER proposal 4 Jul 30th , phone

  5. Resource reduction log M. Tyndel, SPIDER proposal 5 Jul 30th , phone

  6. Bottom-up estimate of effort • ISIS (Andrei) • 7fte (including 0.55 TD design) + £295K = £ 810K • Missing Bristol effort, test beam, travel £250K? • T4DP25 • 5.4fte (including 0.5TD design + 0.5 early) + £60K = £ 450K • Missing TD effort testing, travel £ 50K • TPAC + DCAL • 13.8fte (including 1.8TD design) +£ 410K =£1167K • Over-optimistic £200K • Total =£2427 - £2937 M. Tyndel, SPIDER proposal 6 Jul 30th , phone

  7. Bottom-up estimate of effort • Effort evaluation M. Tyndel, SPIDER proposal 7 Jul 30th , phone

More Related