High-level Power Simulation for DVS-aware Processors

1. Traineeship under supervision of: Prof. H. Corporaal M.Sc. S.V. Gheorghita High-level Power Simulation for DVS-aware Processors by Hans Giesen

2. Overview • Introduction • Design • Implementation • Experiments • Future Work High-level Power Simulation for DVS-aware Processors

3. Overview • Introduction • Design • Implementation • Experiments • Future Work High-level Power Simulation for DVS-aware Processors

4. DVS principle • Energy depends quadratically on supply voltage • Clock frequency depends almost linearly on supply voltage Introduction

5. Deadline Power Idle Time Power Time Real-time embedded systems • Real-time systems have timing constraints Introduction

6. Simulation toolset Max Deadline Combine DVS simulator Power simulator Sample Remove Schedule Statistics Calculate Cycles Introduction

7. Simulation levels Low High System-level analytical models Abstract performance simulation Instruction set simulation Accuracy / Detail Simulation speed Cycle-accurate simulation HDL / RTL simulation High Synthesis Low Introduction

8. Overview • Introduction • Design • Implementation • Experiments • Future Work High-level Power Simulation for DVS-aware Processors

9. XTREM power simulator Input ARM binary Architectureinformation XTREM Performance +energy trace Output Design

10. Intel XScale architecture • Based on ARM architecture • Used in e.g. Intel PXA255 and PXA270 processors Design

11. Simple tracefile example Design

12. Problems for DVS simulation • Trace is only valid for one combination of frequency and voltage • Sample periods have fixed length Design

13. Adapting XTREM Before adaptation: Code After adaptation: Mark Mark Mark Code Design

14. DVS simulator Trace fromXTREM DVS algorithm Architectureinformation DVS simulator Performance +energy trace Design

15. DVS simulator DVS DVS Code Design

16. Overview • Introduction • Design • Implementation • Experiments • Future Work High-level Power Simulation for DVS-aware Processors

17. Deriving power formulas Before: double senseamp_power(int cols) { return((double) cols * Vdd / 8 * .5e-3); } After: double senseamp_power(int cols) { return((double) cols / 8 * .5e-3); } = cV = c Implementation

18. Deriving power formulas Before: power->btb_datapower =ram_decoder_power(logtwo(rowsb), 2) + ram_wordline_power(rowsb, colsb, 1, 1, CACHE) + BTB_DATA_BITLINE_AF * ram_bitline_power(rowsb, colsb, 1, 1, CACHE) +senseamp_power(colsb); After: power->btb_datapower_fV2 = ram_decoder_power(logtwo(rowsb), 2) + ram_wordline_power(rowsb, colsb, 1, 1, CACHE) + BTB_DATA_BITLINE_AF * ram_bitline_power(rowsb, colsb, 1, 1, CACHE); power->btb_datapower_V = senseamp_power(colsb); cfV2 cfV2 cfV2 cV Implementation

19. Power formulas Implementation

20. Example with DVS marks #include <stdio.h> #include "DVS.h" int main() { DVS("Deadline=%u RWEC=%u", 0.026, 3425256); puts("This is a piece of code"); DVS("RWEC=982428"); puts("This is another piece of code"); DVS("%s=%u", "Deadline", 0); } Implementation

21. DVS marks C source of simulated program Call void DVS(const char *iFormat, …) Call int syscall(int number, …) swi instruction XTREM system call interface (syscall.c) DVS_parameters variable XTREM tracefile output (xtrem.c) Implementation

22. Overview • Introduction • Design • Implementation • Experiments • Future Work High-level Power Simulation for DVS-aware Processors

23. Experiments • Comparison of total values of original XTREM and adapted XTREM • Simulation of MP3 decoder • 20 DVS marks • 3 DVS algorithms • 4 Test files Experiments

24. DVS algorithms • Constant algorithm • Similar to using no DVS • Worst Case Execution Path (WCEP) algorithm • At each DVS mark the lowest f and V calculated for which the deadline is still reached in all cases • Oracle algorithm • f and V are calculated using the execution path that must be known in advance Experiments

25. Frequency graph Deadline Deadline Experiments

26. Power graph Deadline Deadline Experiments

27. Total energy consumption Experiments

28. Power distribution Experiments

29. Overview • Introduction • Design • Implementation • Experiments • Future Work High-level Power Simulation for DVS-aware Processors

30. Future Work • Other DVS algorithms • Add more variables to power formulas • Improve accuracy of power simulator Future Work

31. Questions?

32. Thank you for watching