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Basic Microprocessor Timing

Basic Microprocessor Timing. ECE 611 Microprocessor Systems Dr. Roger L. Haggard, Associate Professor Department of Electrical and Computer Engineering Tennessee Technological University Spring 1998. A(23 -1). Valid. Valid. D(15 - 0). Data In. Data In. Addr Valid. Addr Valid. AS*.

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Basic Microprocessor Timing

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  1. Basic Microprocessor Timing ECE 611 Microprocessor Systems Dr. Roger L. Haggard, Associate Professor Department of Electrical and Computer Engineering Tennessee Technological University Spring 1998

  2. A(23 -1) Valid Valid D(15 - 0) Data In Data In Addr Valid Addr Valid AS* LDS* UDS* Enable Data In Enable Data In R/W Read Read Ready Ready DTACK* W W (Must Rise) 68000 Bus Timing - Read States Mem/IO Read (Slow) Mem/IO Read Bus Cycle Bus Cycle S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 W W W W S5 S6 S7 CLK

  3. A(23 -1) Valid Valid D(15 - 0) Data Out Data Out Addr Valid Addr Valid AS* LDS* UDS* Latch Data Latch Data Write Enable Write Enable R/W Ready Ready DTACK* W 68000 Bus Timing - Write Mem/IO Write (Slow) Mem/IO Write Bus Cycle Bus Cycle S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 W W S5 S6 S7 CLK

  4. A(19-16) BHE A,BHE Status A,BHE Status A Data In A Data In AD(15-0) Latch Address Latch Address ALE I/O M / IO Mem RD Read Read Receive Receive DT/R Enable Enable DEN Disable Disable Wait Wait Ready Ready READY AB(19-0) Valid Valid DB(15-0) Data In Data In 8086 Bus Timing - Read Two Wait States States Mem Read I/O Input Bus Cycle Bus Cycle T1 T2 T3 T4 T1 T2 T3 Tw Tw T4 CLK (WR is kept high)

  5. A(19-16) BHE A,BHE Status A,BHE Status AD(15-0) A Data Out A Data Out Latch Address Latch Address ALE Mem I/O M / IO Latch Data Latch Data WR Write Write DT/R Transmit Transmit Enable Enable DEN Disable Disable Wait Ready Ready READY AB(19-0) Valid Valid DB(15-0) Data Out Data Out 8086 Bus Timing - Write One Wait State Mem Write I/O Output Bus Cycle Bus Cycle T1 T2 T3 T4 T1 T2 T3 Tw T4 CLK (RD is kept high)

  6. Machine Cycle S1 S2 S3 S4 S5 S6 S1 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 XTAL2 ALE Enable In Enable In PSEN Port 0 / AD[7-0] A[7-0] out D[7-0] in A[7-0] out D[7-0] in Port 2 / A[15-8] A[15-8] Byte1 A[15-8] Byte2 (if needed) 8051 Timing - Program Memory Read

  7. Machine Cycle 1 Machine Cycle 2 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 XTAL2 ALE Read Inst PSEN Read Data RD (inst) (inst) (data) (data) Port 0 / AD[7-0] A[7-0] out D[7-0] in A[7-0] out D[7-0] in A[7-0] out Port 2 / A[15-8] A[15-8] A[15-8] A[15-8] (inst) (data) 8051 Timing - Data Memory Read

  8. Machine Cycle 1 Machine Cycle 2 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 XTAL2 ALE Read Inst PSEN Write Data WR (inst) (inst) (data) (data) Port 0 / AD[7-0] A[7-0] out D[7-0] in A[7-0] out D[7-0] out A[7-0] out Port 2 / A[15-8] A[15-8] A[15-8] A[15-8] (inst) (data) 8051 Timing - Data Memory Write

  9. Memory Interfacing and Timing

  10. Interface 68000 to 6116 static RAM (1) 11 6116 (2K x8) 16 68000 CPU A(10-0) Address bus Data bus D00- D07 D(7-0) Lower byte A01-A11 RAM1 A(10-0) D08- D15 D(7-0) Upper byte D00- D15 RAM2

  11. Low in a write cycle when AS* also low R/W AS* CS1* LDS* Low during access to RAM1 when LDS* low UDS* CS2* Address decoder A12- A23 RAMCS* low when RAM1or RAM2 addressed Low during access to RAM2 when UDS* low DTACK* DTACK Gen Low when either RAM1 or RAM2 selected delays DTACK* to introduce wait states Interface 68000 to 6116 static RAM (2) R/W OE* 68000 CPU 6116 (2K x8) CS* RAM1 R/W OE* CS* RAM2

  12. A0, BHE* A(11-1) 21 Latch 20 D(7-0) A(19-12) 16 Addr Decoder RAMCS* A0 A(11-1) MEM* D(15-8) BHE* Wait State Gen Interface 8086 to 6116 static RAM 6116 (2K x8) 8086 A(10-0) A ____ BHE D(7-0) __ R/W low byte (even) ALE OE* D CS* A(10-0) __ M/IO D(7-0) __ R/W hi byte (odd) ___ WR ___ RD OE* CS* READY

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