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Microprocessor System Design Processor Timing

Microprocessor System Design Processor Timing. Omid Fatemi (omid@fatemi.net). Outline. Machine cycle Fetch, decode, execute Processor timing Bus cycles Memory / IO read Memory / IO write. Where is a program stored?. ;assume that initially ;ds = 2000, bx = 0023, ax = 351C

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Microprocessor System Design Processor Timing

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  1. Microprocessor System DesignProcessor Timing Omid Fatemi (omid@fatemi.net)

  2. Outline • Machine cycle • Fetch, decode, execute • Processor timing • Bus cycles • Memory / IO read • Memory / IO write

  3. Where is a program stored? ;assume that initially ;ds = 2000, bx = 0023, ax = 351C ;cs = 1000, ip = 0005 mov [bx], al ;8807 hlt ;F4

  4. How does the P works? • Fetch • Increment Program Counter (CS:IP) by 1 • Decode • Execute (if necessary)

  5. FETCH CS:IP

  6. FETCH 1000:0005

  7. FETCH 10005

  8. FETCH 10005 LOW HIGH

  9. FETCH 10005 88 LOW HIGH

  10. FETCH 10005 88 LOW HIGH

  11. INC. PC

  12. INC. PC

  13. DECODE mov [bx], ?

  14. FETCH CS:IP

  15. FETCH 1000:0006

  16. FETCH 10006

  17. FETCH 10006 LOW HIGH

  18. FETCH 10006 07 LOW HIGH

  19. FETCH 10006 07 LOW HIGH

  20. INC. PC

  21. INC. PC

  22. DECODE mov [bx], al

  23. EXECUTE mov [bx], al DS:BX

  24. EXECUTE mov [bx], al 2000:0023

  25. EXECUTE mov [bx], al 20023

  26. EXECUTE mov [bx], al 20023 1C

  27. EXECUTE mov [bx], al 20023 1C HIGH LOW

  28. EXECUTE mov [bx], al 20023 1C HIGH LOW

  29. FETCH CS:IP

  30. FETCH 1000:0007

  31. FETCH 10007

  32. FETCH 10007 LOW HIGH

  33. FETCH 10007 F4 LOW HIGH

  34. FETCH 10007 F4 LOW HIGH

  35. INC. PC 10007 F4 LOW HIGH

  36. INC. PC 10007 F4 LOW HIGH

  37. DECODE 10007 F4 LOW hlt HIGH

  38. EXECUTE hlt

  39. Machine Cycle

  40. Machine Cycle Timing Diagram

  41. Processor Timing

  42. Processor Timing Diagramfor the 1st fetch machine cycle (M1) of instruction mov [bx],al

  43. Processor Timing Diagramfor the 2nd fetch machine cycle (M1) of instruction mov [bx],al

  44. Processor Timing Diagramfor the execute machine cycle (M3) of instruction mov [bx], al

  45. Processor Timing Diagramfor the 1st fetch machine cycle (M1) of instruction hlt

  46. Processor Timing Diagramfor any memory read machine cycle

  47. Processor Timing Diagramfor any memory write machine cycle

  48. Processor Timing Diagramfor any I/O read machine cycle

  49. Processor Timing Diagramfor any I/O write machine cycle

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