Clock Buffer Polarity Assignment Considering Capacitive Load

1. Clock Buffer Polarity Assignment ConsideringCapacitive Load Jianchao Lu and BarisTaskin Electrical and Computer Engineering Drexel University, Philadelphia, PA USA ISPD’10

2. Outline • Introduction • Previous work • Preliminaries • Problem formulation • Methodology • Experimental results • Conclusion

3. Introduction • The power/ground noise manifests itself as the peak current drawn from the supply rails which is hazardous to the circuit operation. • The power and ground noise has a crucial effect on the circuit performance, such as the delay of switching signal. • 0.1V power noise incurs 79.8% delay variation of an inverter (Vdd=0.6, Berkeley Predictive Technology 45nm Model)

4. Introduction • Clock tree has a significant impact on the power/ground noise since all the nodes on the clock tree switch during each cycle. • Reducing the peak current on the chip by reducing the number of simultaneously switching clock sink nodes in a clock tree is called clock buffer polarity assignment.

5. Previous work • Clock buffer polarity assignment for peak current reduction is first introduced by Nieh et. al. [2]. • using opposite-phase buffers Vdd Idd A A Idd Iss Iss Vss

6. Previous work • [4] [5] develop the clock polarity assignment with an algorithm which not only reduces the peak current but also minimizes the skew. • Jang et. al. [6] propose a new polarity assignment method based on [5] that addresses the increased wirelength problem by eliminating the clock tree re-synthesis step while simultaneously considering buffer sizing. None of these previous works consider the effect of the capacitive load for peak current in polarity assignment.

7. Preliminaries • The relationship between peak current and the capacitive load of a clock buffer can be estimated as:

8. Preliminaries

9. Problem formulation • The objective of minimizing the peak current on the supply rails by assigning buffer polarity is formulated as: • Assuming the buffer/inverter of the same size share the same peak current curve. The peak current on the power rail is similar to the peak current on the ground rail for the buffersimulated. The peak current reduction problem is presented as minimizing the peak current on the power rails without loss of generality.

10. Problem formulation • The problem of polarity assignment is actually minimizing the discrepancy of the peak current value of positive polarity buffers and negative polarity buffers. This polarity assignment problem is a number partition problem (NPP) which is a well-known NP-hard problem.The number partition problem is defined as: Given a list a1, a2,...,an of positive integers, find a partition, that is, a subset A, minimizing the discrepancy:

11. Methodology • Polarity Assignment • In general, the NPP problems can be solved by a pseudo-polynomial dynamic programming algorithm.

12. Methodology • Type Assignment • The type assignment method reads the clock tree structure with the polarity assignment • If a clock buffer has the same polarity with its parent, the clock buffer type should be assigned as a buffer. If a clock buffer has a different polarity from its parent, the clock buffer type should be assigned as an inverter.

13. Experimental Results • Benchmark : ISCAS’89 • Synopsys design flow is adopted in experimentsand a 90nm cell library [11] is used in synthesis, extraction and simulation. • Clock tree synthesis is performed using Astro [13].

14. Experimental Results

15. Experimental Results

16. Conclusion • A clock polarity assignment method is proposed which takes into consideration the capacitive load of clock buffers. • The method is able to assign polarity on customized number of levels of the clock tree.