WaveMin : A Fine-Grained Clock Buffer Polarity Assignment Combined with Buffer Sizing

1. WaveMin: A Fine-Grained Clock Buffer Polarity Assignment Combined with Buffer Sizing DeokjinJoo and TaewhanKim School of Electrical Engineering and Computer Science Seoul National University, Korea DAC 2011

2. Outline • Introduction • Previous work[10] • Observations • Problem formulation • Algorithm • Experimental results • Conclusion

3. Introduction • The power/ground noise manifests itself as the peak current drawn from the supply rails which is hazardous to the circuit operation. • This noise also adversely affects circuit performance such as the delay of switching signal.

4. Introduction • The clock buffers consume the current at the clock edges => A large amount of current is generated around the clock edges. • The clock buffers be one of the major sources of power/ground noise. • Reducing the peak current on the chip by reducing the number of simultaneously switching clock sink nodes in a clock tree is called clock buffer polarity assignment.

5. Introdction • Clock buffer polarity assignment Vdd Idd A A Idd Iss Iss Vss

6. Introduction • Clock buffer polarity assignment for power noise reduction Since the leaf buffering elements are the major contributor to the (total) peak current as illustrated by [7], our work also focuses on the polarity assignment on leaf buffering elements.

7. Previous work[10] • Simultaneous polarity assignment and buffer/ inverter sizing for noise minimization while satisfying the clock skew constraint L : set of leaf clock buffering elements B : set of clock buffers in standard cell library I : set of clock inverters in standard cell library κ : skew bound Find the mapping function φ : L → {B∪I } that minimizes the quantities of

8. Observations

9. Problem formulation • Given an available buffer type set B, an inverter type set I, a sub-area that holds set L of leaf buffering elements, time sampling slots S, clock skew constraint κ, find a mapping function φ : L → {B ∪ I} that minimizes the quantity of

10. Algorithm • Since power/ground noise is a local effect, we first divide the circuit into several zones and apply our algorithm to the zones one by one to minimize the peak current at each zone.

11. Algorithm • For each pair of leaf node eiand buffer/inverter type αj , ei ∈ L and αj ∈ B ∪ I, we measure the arrival time to eifrom clock source when φ(ei) = αj . • We arrange the arrival times in non-increasing order: a1, a2, ・ ・ ・ , am, where m = |L|(|B| + |I|) and a1and amare the latest and earliest arrival times, respectively. • Check the feasibility of each time interval [t−κ, t] where t = a1, a2, ・ ・ ・ , am • Then, for each feasible time interval, we apply ClkWaveMinto every zone and minimize the peak current values among the zones. • We then select the solution of the polarity assignment with buffer sizing corresponding to the feasible time interval that gives the minimum peak current among all feasible time intervals.

12. skew bound Algorithm- Check the feasibility of each time interval • From right to left until completely-feasible time interval occurs. completely-feasible not feasible e1 e2 e3 e36 arrival time Period of arrival times to FFs clocked by buffer / inverter

13. Algorithm-ClkWaveMin • Mapping ClkWaveMinto multi-objective shortest path (MOSP) problem • MOSP problem: • Given a directed graph G = (V,A), r dimensional vector weight w ∈ W(a) for each arc a ∈ A and two vertices s, t ∈ V , find all Pareto-optimal paths from s to t, where the cost of a path is defined as the sum of arc weights along the path. • Even for r = 2, it is known that the decision version of MOSP problem is NP-complete [14]. • The MOSP problem can be solved by a fully polynomial ɛ-approximation algorithm devised by Warburton [13].

14. Algorithm-ClkWaveMin

15. Experimental results • The proposed algorithm ClkWaveMin has been implemented in C++ language on a Linux machine and tested on ISCAS’95 benchmark circuits. • The benchmarks were synthesized using Synopsys’ Design Compiler and clock trees were synthesized with IC Compiler, using Nangate45nm Open Cell Library [15]. • RC extractions were performed on IC Compiler and HSPICE simulation was done on the clock trees.

16. Experimental results

17. Experimental results

18. Conclusion • We proposed a completely new (fine-grained) approach to the clock buffer polarity assignment combined with buffer sizing. • We formulated the problem into multi-objective shortest path problem, and proposed fast as well as approximation algorithms to solve the problem.