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Layout Design and the Effect on Maximum Clocking Frequency

Layout Design and the Effect on Maximum Clocking Frequency. By: Jay McDaniel. Project Description. Goals Determine how trace layouts effect propagation delay and maximum clocking frequency Create a lab that could be used for future students Deliverables

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Layout Design and the Effect on Maximum Clocking Frequency

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  1. Layout Design and the Effect on Maximum Clocking Frequency By: Jay McDaniel

  2. Project Description Goals • Determine how trace layouts effect propagation delay and maximum clocking frequency • Create a lab that could be used for future students Deliverables • Design, build, and test circuit used for lab • Lab write-up that includes background information, pre-lab, procedure, and questions

  3. ADS Circuit Schematic

  4. ADS Circuit Simulation

  5. ADS Results • Using D-Type Positive Edge Triggered D Flip Flopswith a tp = 16.5ns and ts = 6.5ns (NC7SV74K8X) • Tmin = 16.5ns + 6.5ns + 1.433ns = 21.433ns => fmax =46.65MHz (straight and curved corner) • Tmin = 16.5ns + 6.5ns + 1.533ns = 21.533ns => fmax = 46.44MHz (90o corner trace) • Leads to a 210KHz slower maximum clocking frequency

  6. Eagle Circuit Schematic

  7. Eagle Circuit Layout

  8. Simulation Results • Straight Trace: fmax = 46.47MHz => tmin = 21.52ns • Curved Trace: fmax = 46.45MHz => tmin = 21.53ns • 90o Trace: fmax = 46.16MHz => tmin = 21.66ns (Note: fmax is 310KHz slower than that for straight trace) • Using straight trace as my control, I found D = .152ns/in (90o trace effective length equal to 10.92”)

  9. Conclusions • Trace layout should either be laid out in a straight fashion or using curved corners to minimize clock frequency reduction • 90o traces can effectively add length to your trace length which in turn adds more delay and reduces your maximum clocking frequency • 90o corner traces should be avoided at all cost but probably inevitable due to vias

  10. Questions?

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