Lecture 22 Delta I DDQ Testing and Built-In Current Testing

1. Lecture 22Delta IDDQ Testing and Built-In Current Testing • Current limit setting • Testing time issues • Delta IDDQ testing (DIDDQ) • Built-in current testing sensors • Summary VLSI Test: Bushnell-Agrawal/Lecture 22

2. Current Limit Setting • Should try to get it < 1 mA • Histogram for 32 bit microprocessor VLSI Test: Bushnell-Agrawal/Lecture 22

3. Scan and Functional Tests Com- pany HP San- dia Scan/ No Funct. 6.04 0.11 Reject Rates (%) Without IDDQ With IDDQ Without IDDQ With IDDQ Neither 16.46 0.80 No Scan/ Funct. 6.36 0.09 Both 5.80 0.00 Functional Tests 5.562 0 Hewlett-Packard / Sandia Laboratories Results • HP – static CMOS standard cell, 8577 gates, 436 FF • Sandia Laboratories – 5000 static RAM tests • Reject rate for various tests: VLSI Test: Bushnell-Agrawal/Lecture 22

4. Failure Distribution in Hewlett-Packard Chip VLSI Test: Bushnell-Agrawal/Lecture 22

5. % Functional Failures After 100 Hours Life Test Work of McEuen at Ford Microelectronics VLSI Test: Bushnell-Agrawal/Lecture 22

6. Lower / Upper IDDQ Test Time Limits – McEuen (Ford) VLSI Test: Bushnell-Agrawal/Lecture 22

7. Delta IDDQ Testing -- Thibeault • Use derivative of IDDQ at test vector as current signature DIDDQ (i) = IDDQ (i) – IDDQ (i – 1) • Leads to a narrower histogram • Eliminates variation between chips and between wafers • P – probability of false test decisions VLSI Test: Bushnell-Agrawal/Lecture 22

8. IDDQ Versus DIDDQ VLSI Test: Bushnell-Agrawal/Lecture 22

9. Difference in Histograms • A – test escapes, B – yield loss VLSI Test: Bushnell-Agrawal/Lecture 22

10. IDDQDIDDQ Dist. Param P mg Ddef mb s2 Symbol Piddq mgi Ddef mgi + Ddef si2 Ddef 0.3 0.4 0.5 Value Below 0.696 0.4 1.096 0.039 Piddq 0.059 0.032 0.017 Symbol Pdelta mgd(0) Ddef mgd + Ddef sd2 Pdelta 7.3e-4 4.4e-5 1.7e-6 Value Below -2e-4 0.4 0.4 0.004 Piddq / Pdelta 81 721 10000 Values of P for different Ddef Values Parameters for Estimating P Ddef -- minimum | DIDDQ | peak from active defect, mg = good mean, mb = bad mean VLSI Test: Bushnell-Agrawal/Lecture 22

11. Example Differential IDDQ Histogram • Better peak resolution with | DIDDQ (i) |, doubles point count VLSI Test: Bushnell-Agrawal/Lecture 22

12. DIDDQ 3.5e-3 2.1e-3 Pdelta = 5.6e-3 Item RYL (yield loss ratio) RTE (test escape ratio) P (= RYL + RTE) Gain in test quality IDDQ 4.4e-4 1.8e-1 Piddq = 1.8e-1 Piddq / Pdelta = 31 DIDDQ Testing Results VLSI Test: Bushnell-Agrawal/Lecture 22

13. IDDQ Built-in Current Testing – Maly and Nigh • Build current sensor into ground bus of device-under-test • Voltage drop device & comparator • Compares virtual ground VGND with Vrefat end of each clock – VGND > Vref only in bad circuits • Activates circuit breaker when bad device found VLSI Test: Bushnell-Agrawal/Lecture 22

14. Conceptual BIC Sensor VLSI Test: Bushnell-Agrawal/Lecture 22

15. CMOS BIC Sensor VLSI Test: Bushnell-Agrawal/Lecture 22

16. Setting Optimal # Transistors in Block • Must partition chip into functional units, each with its own BIC • Too large a unit – combined leakage currents erroneously trigger BIC sensor • Idefmin – smallest defect current • Inoisemax – maximum noise-related peak supply current • Minimum area sensor design at Idefmin and IDDQ intersection • Nmax – maximum # transistors in 1 BIC unit VLSI Test: Bushnell-Agrawal/Lecture 22

17. Graph for Choosing Nmax VLSI Test: Bushnell-Agrawal/Lecture 22

18. Summary • IDDQ current limit setting to differentiate between good and bad circuits is difficult • IDDQ testing is becoming more problematic • Greater leakage currents in MOSFETs in deep sub-micron technologies • Harder to discriminate elevated IDDQ from 100,000 transistor leakage currents • DIDDQ holds promise to alleviate problems • Built-in current testing holds promise VLSI Test: Bushnell-Agrawal/Lecture 22