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Test Based on Current Monitoring: I DDq Testing

Test Based on Current Monitoring: I DDq Testing. Up to now, fault-tolerance has been based on the observation of system logic states . The next slides describe a new paradigm: decide if the system is correct or faulty by observing the current ( I DDq ) consumption .

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Test Based on Current Monitoring: I DDq Testing

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  1. Test Based on Current Monitoring: IDDq Testing vargas@computer.org

  2. Up to now, fault-tolerance has been based on the observation of system logic states. The next slides describe a new paradigm: decide if the system is correct or faulty by observing the current (IDDq) consumption. This approach is also based on HW redundancy, since extra logic is placedon-boardor on-chip in the form of dedicated chips or IP-cores, respectively. vargas@computer.org

  3. What is IDDq? Em 1963 Frank Wanlass (FairchildSemiconductor) publicou o conceito de circuito CMOS. Ocorreu-lhe que um circuito CMOS usa muito pouca potência quando em standby, na verdade a única corrente que fluiria seria a corrente deleakage. vargas@computer.org

  4. What is IDDq? Reference Paper: Mark W. Levi in his ITC’1981 paper (“CMOS is most Testable”, Proceedings of ITC’81, pp. 217-220). vargas@computer.org

  5. What is IDDq? FaultyBehavior vargas@computer.org

  6. What is IDDq? FaultyBehavior vargas@computer.org

  7. What is IDDq? Mede a corrente de entradaem condição de steady state. Nenhum caminho direto entre VDD e Gnd. Sem defeito -> alta impedância entre VDD e Gndno estado quiescente! Se o IC puxa corrente -> defeito! vargas@computer.org

  8. Dificulties involved with IDDq Monitoring • Determinar o threshold • Muito alto (qual o problema?) • Muito baixo (qual o problema?) vargas@computer.org

  9. Dificulties involved with IDDq Monitoring vargas@computer.org

  10. Dificulties involved with IDDq Monitoring • Devemos jogar todos os CIs com IDDq anormal no lixo, mesmo que passem em outros tipos testes? • Sim ! vargas@computer.org

  11. Types of Defects Detected by IDDq Monitoring vargas@computer.org

  12. IDDq and Technology Scaling • O teste de IDDQ é mais difícil para 130-nm ou processos menores, porque o ruído no circuito dificulta a distinção entre o dispositivo bom e o com falha. vargas@computer.org

  13. IDDq Fault Coverage Goal: IDDQ fault coverage of 95% or greater vargas@computer.org

  14. Techniques for Measurements (1) • Módulos Monitores On-Board • Chips monitores que são colocados na placa vargas@computer.org

  15. Techniques for Measurements (1) • Módulos Monitores On-Board • Chips monitores que são colocados na placa vargas@computer.org

  16. Techniques for Measurements (1) • Módulos Monitores On-Board • Chips monitores que são colocados na placa On-Board Test Controller (or Automatic Test Equipment ) Synchronization vargas@computer.org

  17. Techniques for Measurements (2) • Módulos Monitores On-Chip • Núcleos IP monitores que são colocados on-chip ICCD 1988 vargas@computer.org

  18. Techniques for Measurements (2) • Módulos Monitores On-Chip • Núcleos IP monitores que são colocados on-chip vargas@computer.org

  19. Techniques for Measurements (2) • Módulos Monitores On-Chip • Núcleos IP monitores que são colocados on-chip vargas@computer.org

  20. Techniques for Measurements (2) • Módulos Monitores On-Chip • Núcleos IP monitores que são colocados on-chip vargas@computer.org

  21. Techniques for Measurements (3) vargas@computer.org

  22. Techniques for Measurements (3) 1K x 1bit SEU-Tolerant SRAM Chip with Core Size: 3.5 X 4.6mm2 vargas@computer.org

  23. Thank you for your attention vargas@computer.org

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