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2010.05.14 Presenter: PCLee

A Reconfigurable Design-for-Debug Infrastructure for SoCs author: Miron Abramovici , Paul Bradley, Kumar Dwarakanath , Peter Levin, Gerard Memmi , Dave Miller DAFCA, Inc. DAC 2006. 2010.05.14 Presenter: PCLee. Abstract .

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2010.05.14 Presenter: PCLee

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  1. A Reconfigurable Design-for-DebugInfrastructure for SoCsauthor: MironAbramovici, Paul Bradley, Kumar Dwarakanath, Peter Levin, Gerard Memmi, Dave MillerDAFCA, Inc. DAC 2006 2010.05.14 Presenter: PCLee

  2. Abstract • In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters.

  3. Introduction • What’s the problem: • 2/3 errors escape from pre-silicon debug. • Lack of standard methodology and DFD infrastructure for silicon debug. • Lack of internal observation is challenge. • The proposed method • Distributed reconfigurable fabric • Inexpensive DFD instrument

  4. Related work Architectures and Algorithms for Synthesizable Embedded Programmable Logic[9] DfD: catching design errors in digital chips[10] Commercial EDA tools for first silicon debug[1][8] Increase reusability Increase observability This paper Hierarchical Embedded Logic Analyzer for Accurate Root-Cause Analysis

  5. DfD instrument in SoC Signal Probe Network(SPN): collect signal to other instrument Tracer: record input signals Debug Monitor(DEMON): analyze signal(modified) Wrapper: analyze signal(non-modified) CapStim: a tracer whose memory may be preloaded with vectors

  6. Reconfigurable hardware • Reconfigurable hardware contains: • Look-up tables • Flip-flops • Routing MUXex • PTE(Programmable trigger engine): specialized instrument to implement FSMs.(trade-off) • etc… • User-specified instrument model • Number of inputs, outputs and states • Number of n-bits comparators and counters • etc…

  7. Debug Paradigms-1, 2 • Signal capture: • Assertion-based debug: • Configure in DEMON • Automatic check the root-cause of errors • Improve observability of internal errors • Partition assertions into group, download a group at a time • As a event trigger Watch waveform on VERDI Configure CAPTURED SIGNAL DEMON TRACER SELECTED SIGNAL DUMP SIGNAL terminal Mux of SPN Start or stop

  8. Debug Paradigms-3 • Event-driven analysis • Use SoC event to initiate debug activities • Example: request->ack->grant • For in-system debug, error occur at different clock cycles. • Transaction can be easily to trace.

  9. Debug Paradigms-4, 5 • Stimulate-and-capture • CapStim’s buffer contains stimuli to other functional block. • Upload vectors of buffer using JTAG • After an vector have been applied, the output replace the vector. • What-if experimentation • Override system signals in wrappers. • Force some signals to a constant value, then check by DEMON. bus target functional block 2 3 SPN CapStim 2 1 Event trigger

  10. Other applications • Performance measurements • Counting transaction as a event • Determine latency of a bus transfer • Cache miss or hit at a specified interval • On-line testing • For mission-critical application • Run-time configure many groups of assertions • Soft error-fixing • Some signals corrected at wrapper by simple combinational function.

  11. Necessary signals • NEW IP cores • Logic block have been fully verified by formal verification. • Still fail in silicon, because process variation • We would like to check high-risk areas. • Control logic of interconnected FSMs • Important and complex transactions • Wrapping a signal has more impact on timing and area

  12. Experiment result • PERSONALITY EDITOR: • Low-level access to functions of look-up table and routing structures • Create debug structures • User can access libraries of common hardware structures • FSM described in a simple language • Verilog models for modeling debug hardware • EXPERIMENTAL CHIP • LEON processor • Designed at university of Tennessee • Manufactured by MOSIS

  13. Conclusion • Conclusion of this paper: • This paper introduced a distributed reconfigurable fabric based DFD methodology. • Can implement many debug structures and paradigm • My conclusion: • The application for their DfD is good to utilize. • They use the wrapper to analyze signal is good point.

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