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Compaction and pattern drop

This presentation discusses compaction and pattern dropping techniques to reduce test pattern size and improve coverage in combinational logic circuits. The algorithm overview, implementation details, and experimental results are presented.

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Compaction and pattern drop

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  1. Compaction and pattern drop Intaik Park Ahmad Al-Yamani RATS (Reliability and Testability Seminar) Intaik Park, RATS, Fall 2004

  2. Outline • Introduction • Algorithm overview • Implementation • Experimental result Intaik Park, RATS, Fall 2004

  3. Introduction • Current issue: test pattern size too big • Compaction • Pattern dropping • Limitations • Compaction – pattern size still big • Pattern dropping – coverage drop Intaik Park, RATS, Fall 2004

  4. Motivation • Need to compact as much as possible • Want to drop pattern with less coverage drop • Exploit don't-care terms Intaik Park, RATS, Fall 2004

  5. Outline • Introduction • Algorithm overview • Implementation • Experimental result Intaik Park, RATS, Fall 2004

  6. Algorithm overview 1. Compare patterns 2. similar patterns? regenerate one pattern  compatible with the other 3. Merge patterns Intaik Park, RATS, Fall 2004

  7. Definitions • Distance between patterns • Number of different care bits • Essential faults • Faults that are only detected by a certain pattern Intaik Park, RATS, Fall 2004

  8. Regeneration • Pattern A: 0 1 X X X 1 1 X X X 0 • Pattern B: 1 1 X X X 0 X 1 X X X  (Distance: 2) • Regenerate Pattern B • Pattern A : 0 1 X X X 1 1 X X X 0 • Pattern B' : 0 1 X X X 1 1 1 X X 0 • Now compatible Intaik Park, RATS, Fall 2004

  9. Pattern distance graph Pat B 2 Pat A 3 7 3 Pat C 8 1 2 9 5 Pat E Pat D Intaik Park, RATS, Fall 2004

  10. Essential Faults • Pattern A: fault f1, f2 • Pattern B: fault f3, f4 • Pattern C: fault f1, f4, f5 • Essential faults for Pattern A : f2 • Essential faults for Pattern B : f3 • Essential faults for Pattern C : f5 Intaik Park, RATS, Fall 2004

  11. Essential Faults (contd.) • Pattern A: fault f1, f2 • Pattern B: fault f3, f4 • Pattern C: f1, f4, f5 • If Pattern B' covers fault f1, f2, f3 • no fault coverage drop • If Pattern B' covers fault f1, f2, f4 • fault f3 missed Intaik Park, RATS, Fall 2004

  12. Outline • Introduction • Algorithm overview • Implementation • Experimental result Intaik Park, RATS, Fall 2004

  13. Implementation • Commercial ATPG tool (regeneration) • PI and cell constraints • Perl script and C++ (pattern compare and setup generation) Intaik Park, RATS, Fall 2004

  14. flowchart Start Merge patterns with least coverage drop CheckDistances between pattern pairs Pattern size Small enough? Regenerate patterns with small distance No Yes End Intaik Park, RATS, Fall 2004

  15. Outline • Introduction • Algorithm overview • Implementation • Experimental result Intaik Park, RATS, Fall 2004

  16. Experimental circuits Intaik Park, RATS, Fall 2004

  17. Result on LSI2901 Intaik Park, RATS, Fall 2004

  18. Result on Bmatch Intaik Park, RATS, Fall 2004

  19. Result on 8051 Intaik Park, RATS, Fall 2004

  20. Conclusion • Shrink test pattern size with less affect on coverage • Works better with... • Large design • Scan-inserted design • Need transition fault flow • Use essential faults in regeneration Intaik Park, RATS, Fall 2004

  21. Reference [1] Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits - Kajihara, Kinoshita, M. Reddy 1995 [2] On Compacting Test Sets by Addition and Removal of Test Vectors - Kajihara, Pomeranz, Kinoshita, M. Reddy - 1994 IEEE Intaik Park, RATS, Fall 2004

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