X-Compaction

1. X-Compaction Itamar Feldman

2. Before we begin… Let’s talk about some DFT history: Design For Testability (DFT) has been around since the 1960s. The technology was developed to reduce the cost of creating a successful test for an IC. Scan Technology • memory elements (flip-flops) of the design are put into a shift register. • These memory elements could be set to a logic 1 or logic 0, and the values captured in them could be observed. Numerous refinements were developed on this technology - • Partial scan, boundary scan and wrappers all use the fundamental scan technology, BIST , ATPG algorithm and more.

3. Where is DFT heading? New Challenges and Trends: • The scaling of process technology -> significant changes. • New test challenges have appeared, requiring new solutions in DFT. • Industry has redirected its focus to optimizing test-data-volume and test-application-time. • Scan chains, the very technology that enables DFT, now pose a new challenge. • Scan chains become very long, and the time required to process the scan chains has increased.

4. Scan Chains

5. processing a scan test pattern Typical sequence in processing a single scan test pattern: • Set up the scan chain configuration. • Shift values into the active scan chains. • Exit the scan configuration. • Apply stimulus to the test circuit inputs and measure the outputs. • Pulse clocks to capture the test circuit response in flip-flops. • Set up the scan chain configuration. • Shift values out of the active scan chains. • Exit the scan configuration. The shift operations use as many clock periods as the longest scan chain!.

6. The Solutions • creative ways to treat the randomly filled bits. • minimize the amount of intrusion in the design • optimize the test-data-volume and test-application-time • test process can be streamlined and compacted.

7. Solution info

8. Outline • Introduction • Overview of X-Compact • Coverage of errors in the presence of X’s • DPM impact for Actual designs • Conclusions

9. INTRODUCTION Outline: Introduction Overview of X-Compact Coverage of errors in the presence of X’s DPM impact for Actual designs Conclusions

10. X-Compaction Introduction • We present a technique to compact test response data using combinational logic circuits. • Compact the Output results whilst retaining the DFT capabilities of the chip • reducing the time needed to analyze the results exponentially • guarantee detection of defective chips even in the presence of unknown logic values.

11. X-Compaction advantages • Improving test quality • Non-intrusive • Very little hardware overhead • No special configure is needed • X-tolerance • Reduce Number of scanout pins almost exponentially. • Reduce Number of scan channels • Reduce Scan test data volume Shorten scan test time

12. OVERVIEW Outline: Introduction Overview of X-Compact Coverage of errors in the presence of X’s DPM impact for Actual designs Conclusions

13. X-Compaction approach

14. Basic idea • The X-Compactor circuit block is a combinational circuit made up of XOR gates. • Let us suppose that we have a design with n scan chains. • Suppose that the X-Compactor has m outputs. • The X-Compactor circuit can be represented as a binary matrix with n rows and m columns • This matrix is called the X-Compact matrix

15. Example of X-Compactor circuit m n In this Example the first output is obtained by XORing the outputs of 1,2,3,4,5 and 6 according to the X-Compact Matrix, As you can see in the above circuit

16. X-Compaction matrix • Each row of the matrix • corresponds to a scan chain. • Each column corresponds to a • compactor output. • The entry in row i and column j of the X-Compact matrix is 1 iff the jth compactor output depends on the output ofthe ith scan chain; otherwise, the entry is 0.

17. Error detection capabilities Error detection capability of X-Compact circuits: • The X-Compactor HW will detect 1,2,3 and any odd number of errors without any X values present. • The X-Compactor HW will detect one error in the present of a single X value generated simultaneously. The above properties of X-Compactor circuits were proved in [Mitra 02a].

18. X-Values, the problem. • Xor-ing with a X-value gives a X-value, and an error can be undetected. • Xor-ing while compacting can cause data signature corruption • Several solutions: well managed X-compact matrices, higher m ratio, and X-Tolerance.

19. Output pins Reduction The fallowing table shows the number of X-Compact output pins in compared to the original Scan Chain number. Exponential reduction! (x240 reduction) ->

20. Error detection in a presence of X-values Outline: Introduction Overview of X-Compact Coverage of errors in the presence of X’s DPM impact for Actual designs Conclusions

21. Error detection in a presence of X-values • The X-Compactor design guarantee detection of an error when a scan chain produces error and another produces X. • This doesn’t necessarily mean when a scan chain produces error and two or three scan chains produce X’s that the error will not be detected! • It really depends on which scan chain produced the error and which scan chains produced 2 or 3 X’s. • What is the probability that an error will not be detected when 2 or 3 (or more) scan chains produce X’s?

22. Analysis of X-compaction • The probability that an error produced by a scan will not be detected when k other scan chains produce Xs simultaneously is denoted by p(n, k, i). • Where n is the number of uncompacted ouputs and i is the number of 1’s in the matrix rows for the practical use of the analysis we’ll use 2 & 3

23. Percentage of undetected errors in the Presence of X values Tables 3.1-3.2 show the values of p(n, k,2) and p(n, k, 3) for various values of n and k.

24. DPM impact Outline: Introduction Overview of X-Compact Coverage of errors in the presence of X’s DPM impact for Actual designs Conclusions

25. X-Compaction impact on DPM • Let Y be the yield of the part. (1-Y) is the proportion of parts that are defective. • If C is the proportion of defective chips detected by the regular scan test, the number of defective chips that will escape is (1-Y)*(1-C) and the resulting customer DPM is

26. Impact on DPM cont. If z is the proportion of detected defective chips cannot be detected due to the presence of the X-Compactor, then the resulting DPM is: For 80% yield and a test quality of 100 DPM without X-Compactor, the DPM is: For all practical reasons Z<<1

27. X-distribution effect on DPM in Actual designs Outline: Introduction Overview of X-Compact Coverage of errors in the presence of X’s DPM impact for Actual designs Conclusions

28. Actual designs Actual Design for X-Compact implementation differ in several issues: • X-management – What % of X-values are we expecting to have • Ratio of n/m (Uncompacted/compacted outputs) • X-Compact Matrices (will be covered in X-tolerance)

29. Measurement Analysis Design for X-Compact are measured in: • Percentage of detected error. • DPM impact on production. • Number of cycles for Test. • X-tolerance.

30. Actual Designs We will look at 3 designs • Moderate X-Management (86% without X values) • Well-Managed X (98% without X values) • ILL-Managed X (74% without X values) For each case will look into several values for m and it’s effect on DPM.

31. Design1 Moderate X-Management 86% of all scan-out cycle don’t produce X-values • Desing1 with n=400,m=31 (Type1) ~98.5% of defective chip detection for no or a single X tolerant, impact on DPM < 0.02 • m=20 impact on DPM < 0.13 (Type2) • m=11 Serial scan only 1X Tolerance allowed per scan, (37 cycles), 24 time reduction in test time!, no impact on DPM!

32. Design2 Well-Managed X 98% of all scan-out cycle don’t produce X-values • Desing2 with n=400,m=31 (Type1) ~99.36% of defective chip detection for no or a single X tolerant, impact on DPM < 0.16 • m=20 impact on DPM < 0.3 (Type2) • m=11 Serial scan only 1X Tolerance allowed per scan, (37 cycles), 14.7 time reduction in test time!, no impact on DPM!

33. Design3 ILL-Managed X 74% of all scan-out cycle don’t produce X-values • Desing3 with n=400,m=31 (Type1) ~95.8% of defective chip detection for no or a single X tolerant, impact on DPM < 0.77 • m=20 impact on DPM < 1 (Type2) • m=11 Serial scan only 1X Tolerance allowed per scan, (37 cycles), 30 time reduction in test time!, no impact on DPM!

34. One Assumption • This analysis assumes that there is no correlation between how X’s and errors appear in the two scan-out cycles. • In case there is The DPM impact due to the correlation is could be much higher (up to x4 in ILL-Managed!) and unacceptable • In this case the user can use the technique with serial scan support.

35. Conclusion Outline: Introduction Overview of X-Compact Coverage of errors in the presence of X’s DPM impact for Actual designs Conclusions

36. Conclusion • We can clearly see the usefulness of the X-Compact technique for response compaction purposes. • This technique can save time, space and has little overhead for it’s HW. • It is also shown that X-Compactor designs with none, or few X values has little or no effect on DPM and will save time.

37. Q&A

38. Thanks for listening! Based on an article by Subhasish Mitra*, Kee Sup Kim and Shyam Kallepalli / 15-Oct-2002 “Analysis of Practical X-Compact Designs”