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Using Standard HDL Interfaces for IP Core Testing

Using Standard HDL Interfaces for IP Core Testing. System-on-Chip (SoC) Reusable Cores Core Types Soft Firm Hard Intellectual Property (IP). SoC Testing. Core-Level Testing Chip-Level Testing SoC Testing Present Solutions Test Bus Core Transparency Test Wrappers.

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Using Standard HDL Interfaces for IP Core Testing

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  1. Using Standard HDL Interfaces for IP Core Testing • System-on-Chip (SoC) • Reusable Cores • Core Types • Soft • Firm • Hard • Intellectual Property (IP)

  2. SoC Testing • Core-Level Testing • Chip-Level Testing • SoC Testing Present Solutions • Test Bus • Core Transparency • Test Wrappers

  3. Soc Testing with VPI • Hardware Description Languages (HDLs) • VHDL Procedural Interface (VHPI) • Verilog Procedural Interface (VPI) • VPI Environment • Fault Simulation with VPI • Proposed VPI Tasks : $NodeList, $FaultList, $CounterVector, $SaveOutput, $FaultInjection, $CompareOutput • Test Generation using VPI • Proposed VPI Tasks: $NodeList, $FaultList, $ReadStatus, $RandomVector, $SaveOutput, $RestoreStatus, $FaultInjection, $CompareOutput

  4. VPI Environment • Core and Test-bench in Verilog • VPI Tasks in C including vpi_user.h • Simulation under a VPI Simulator

  5. Fault Simulation Environment

  6. Test Generation Environment • Combinational Design • Random Vectors • Sequential Design • Random Block of Vectors • Save Design Status • Decide to keep the Block of Vectors • Restore the Design Status if Needed

  7. Future Works • Where we are? • PARWAN as an example • Serial Fault Simulation • Test Generation using Proposed Algorithm • What is next? • More Test-benches • Other Fault Simulation Algorithms such as Concurrent, Deductive, a combination of them or even a new VPI-based Algorithm • Come up with a VPI-based Test Generation algorithm with higher performance

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