Objectives

1. PROGRAMMABLE LOGIC DESIGN WITH VHDLEric Deng ( hai tao )Field Applications EngineerCypress Semiconductoredx@cypress.com

2. Objectives • You will learn enough about VHDL to: • Design efficient combinatorial and sequential logic • Design state machines and understand implementation trade-offs • Design using multi-level hierarchy • Identify how VHDL will synthesize and fit into a PLD or CPLD

3. Objectives (contd.) • You will learn enough about the Warp software to: • Compile and synthesize VHDL designs for programmable logic devices • Target PLDs/CPLDs • Simulate the resulting device functionality in Nova • Use the report file to determine operating frequency, set-up time, clock to output delay, and device resource usage.

4. VHDL Design Descriptions The Entity, Ports, Modes, Types Exercise #1 The Architecture, Architecture Styles VHDL Statements, Combinatorial Logic Processes, Signals Vs. Variables VHDL Operators/Overloading/Inferencing VHDL Identifiers Exercise #2 MORNING BREAK Using Warp Exercise #3 Registered Logic Implicit Memory LUNCH Exercise #4 State Machines and State Encoding Exercise #5 AFTERNOON BREAK Hierarchical Designs Exercise #6 Miscellaneous Topics Summary and Conclusion Agenda

5. What is VHDL ? VHSIC (Very High Speed Integrated Circuit) Hardware Description Language • VHDL is a Design Description Language • VHDL is a Design Documentation Language • VHDL is a Simulation Language • It is an IEEE Standard Language (IEEE1076 & 1164)

6. Why Use VHDL? • Very Fast Time-to-Market • Allows designers to quickly develop designs requiring tens of thousands of logic gates or more • Provides powerful high-level constructs for describing complex logic • Supports modular design methodology and multiple levels of hierarchy • One language for design and simulation • Allows creation of device-independent designs that are portable to multiple PLD vendors • Allows user to pick any synthesis tool, vendor, or device

7. VHDL Design Descriptions • VHDL design descriptions consist of an ENTITY declaration and an ARCHITECTURE body • The ENTITY declaration describes the design I/O • The ARCHITECTURE body describes the content or function of the design • Every architecture needs an entity so it is common to refer to them together as an ENTITY/ARCHITECTURE PAIR

8. The Entity • A “BLACK BOX” • The ENTITY describes the I/O of the black box BLACK_BOX rst q[7:0] d[7:0] co clk

9. BLACK_BOX rst q[7:0] d[7:0] co clk Example Entity declaration ENTITY black_box IS PORT ( clk, rst: INstd_logic; d: INstd_logic_vector(7 DOWNTO 0); q: OUTstd_logic_vector(7 DOWNTO 0); co: OUTstd_logic); END black_box; • What does it all mean ?

10. Ports • The Entity (“BLACK BOX”) has PORTS • PORTS are the points of communication • PORTS are usually the device pins • PORTS have an associated name, mode, and type

11. Port Modes A port’s MODE indicates the direction that data is transferred: • IN Data goes into the entity only • OUT Data goes out of the entity only (and is not used internally) • INOUT Data is bi-directional (goes into and out of the entity) • BUFFER Data that goes out of the entity and is also fed-back internally Entity

12. IEEE 1076 Types • Every port on the entity has a Type. The type is always checked during an assignment or comparison. • BIT - a port of type bit that can only take values of '0' or '1' • BIT_VECTOR - a grouping of bits (each can be '0' or '1') ENTITY type_example IS PORT ( a: IN BIT; b: OUTBIT_VECTOR(0 TO 3); -- ascending range c: OUTBIT_VECTOR(3 DOWNTO 0); -- descending range END type_example; b <= "0111"; -- Note: <= is an assignment c <= "0101"; -- double quotes (“”) used for vectors This means that: b(0) = '0' c(0) = '1' b(1) = '1' c(1) = '0' b(2) = '1' c(2) = '1' b(3) = '1' c(3) = '0'

13. IEEE 1076 Types (contd.) • INTEGER • useful as index holders for loops, constants, arithmetic functions, or simulation modeling • BOOLEAN • can take values ‘TRUE’ or ‘FALSE’ • ENUMERATED • has user defined set of possible values. e.g.: TYPE traffic_light IS (red, yellow, green);

14. IEEE 1164 • A package created to solve the limitations of the BIT type • Nine values instead of just two ('0' and '1') • Allows increased flexibility in VHDL coding, synthesis, and simulation • STD_LOGIC and STD_LOGIC_VECTOR are used instead of BIT and BIT_VECTOR when a multi-valued logic system is required • STD_LOGIC and STD_LOGIC _VECTOR must be used when tri-state logic (Z) is required • To be able to use this new type, you need to add 2 lines to your code: LIBRARY ieee; USE ieee.std_logic_1164.ALL;

15. IEEE-1164 Types • STD_LOGIC and STD_LOGIC_VECTOR arenowthe industry standard logic type for digital design • All 9 values are valid in a VHDL simulator, however only: • ‘0’ -- Hard ‘0’ • ‘1’ -- Hard ‘1’ • ‘Z’ -- High Impedance • ‘L’ -- Weak ‘0’ (like resistor pull down) • ‘H’ -- Weak ‘1’ (like resistor pull up) • ‘-’ -- Don’t care are recognized for logic synthesis

16. BLACK_BOX MODE TYPE rst q[7:0] d[7:0] co clk Entity Declaration Example LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY black_box IS PORT ( clk, rst: INstd_logic; d: INstd_logic_vector(7 DOWNTO 0); q: OUTstd_logic_vector(7 DOWNTO 0); co: OUTstd_logic); END black_box;

17. Exercise #1: The Entity • Write an entity declaration for the following: Port D is a 12-bit bus, input only Port OE and CLK are each input bits Port AD is a 12-bit bi-directional bus Port A is a 12-bit bus, output only Port INT is an output Port AS is an output also used internally my_design ad[11:0] d[11:0] a[11:0] oe int clk as

18. my_design ad[11:0] d[11:0] a[11:0] oe int clk as Exercise #1: Solution LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY my_design IS PORT ( d: IN std_logic_vector(11 DOWNTO 0); oe, clk: IN std_logic; ad: INOUT std_logic_vector(11 DOWNTO 0); a: OUT std_logic_vector(11 DOWNTO 0); int: OUT std_logic; as: BUFFER std_logic); END my_design; -- In this presentation, VHDL keywords -- are highlighted in bold, CAPITALS. -- However, VHDL is not case sensitive: -- clock, Clock, CLOCK all refer to the -- same signal

19. The Architecture • Architectures describe what is in the black box (i.e. the function or behavior of entities) • Descriptions can be either a combination of • Structural descriptions • Instantiations of building blocks (placement of componentsjust like a schematicand their connections) • Behavioral descriptions • Algorithmic (or “high-level”) descriptions: IF a = b THEN state <= state5; • Boolean equations: x <= (a OR b) AND c;

20. Behavioral Architecture Example • 2x 8 Input AND gate: ENTITY black_box IS PORT ( a, b: INstd_logic_vector(7 DOWNTO 0); y: OUTstd_logic_vector(7 DOWNTO 0)); END black_box; ARCHITECTURE example OF black_box IS BEGIN y <= a AND b; END example; • This example shows how to drive the device pins (the entity ports). How do we handle internal signals (or nets) that do not connect directly to the device pins ?

21. Signals • Typically used to represent wires (or nets) • Entity Ports are a special type of signal • Like ports, they have a name and type (however, there is no mode) • Signals are declared inside the architecture before the BEGIN • For Example, to create an internal 4 bit bus: ARCHITECTURE signal_example OF black_box IS SIGNAL count: std_logic_vector (3 DOWNTO 0); BEGIN .. <Many VHDL Statements> END signal_example; • Let’s learn some basic VHDL statements…..

22. Combinatorial Logic • There are many ways to describe combinatorial circuits • In the next few slides, we will take a look at some examples of how to describe combinatorial logic • You should refer back to these slides for some ideas when you start writing your first designs

23. s 2 a x b mux c d VHDL Statement Examples (1) Boolean Equations • All standard Boolean operators are supported in VHDL • AND, OR, NOT, XOR, XNOR, NAND • For example, a 4-1 multiplexer is shown below x <= (a AND NOT(s(1)) AND NOT(s(0))) OR (b AND NOT(s(1)) AND s(0)) OR (c AND s(1) AND NOT(s(0))) OR (d AND s(1) AND s(0)) ;

24. VHDL Statement Examples (2) WITH-SELECT-WHEN • Assignment based on a selection signal • WHEN clauses must be mutually exclusive (all different) • Always use “WHEN OTHERS” to cover unspecified cases • Only one reference to the signal, only one assignment operator (<=) WITH selection_signal SELECT signal_name <= value_1 WHEN value_1 of selection_signal, value_2 WHEN value_2 of selection_signal, ... value_n WHEN value_n of selection_signal, value_x WHEN OTHERS;

25. s 2 a x b mux c d VHDL Statement Examples (2) WITH-SELECT-WHEN • The same 4-1 multiplexer we saw earlier could also be described as follows: WITH s SELECT x <= a WHEN “00”, -- means when s=“00” b WHEN “01”, c WHEN “10”, d WHENOTHERS;

26. VHDL Statement Examples (2) WITH-SELECT-WHEN • There can be multiple conditions on each line: WITH s SELECT x <= a WHEN ”000” | “001” | “010”, b WHEN "101" | "111", -- ‘|’ means “or” in this case c WHENOTHERS;

27. VHDL Statement Examples (3) WHEN- ELSE • Signal is assigned a value based on conditions • Any simple expression can be a condition • Priority goes in order of appearance • Only one reference to the signal, only one assignment operator (<=) • Always end with ELSE to cover unspecified conditions signal_name <= value_1 WHEN condition1 ELSE value_2 WHEN condition2 ELSE ... value_n WHEN conditionn ELSE value_x;

28. s 2 a x b mux c d VHDL Statement Examples (3) WHEN-ELSE • The same example 4-1 multiplexer could also be described as follows: x <= a when (s = “00”) else b when (s = “01”) else c when (s = “10”) else d ;

29. VHDL Statement Examples (3) WHEN-ELSE • What is the difference between WITH-SELECT-WHEN and WHEN-ELSE ? • WITH-SELECT-WHEN allows only one control signal • WHEN-ELSE supports many different control signals • Example: A priority encoder j <= w when (a = ‘1’) else x when (b = ‘1’) else y when (c = ‘1’) else z when (d = ‘1’) else ‘0’ ;

30. VHDL Statements • There are two types of statements, Concurrentand Sequential • Concurrent Statements(means in parallel) • Concurrent statements are “executed” concurrently (at the same time) • The examples we have seen so far are all concurrent statements: • Boolean Equations • WHEN-ELSE • WITH-SELECT-WHEN • The order of concurrent statements is not important

31. The order of concurrent statements • For example, suppose we had the following 2 lines of code: x <= a OR b OR c; y <= x WHEN (e=‘1’) ELSE ‘0’; • This will produce exactly the same result as: y <= x WHEN (e=‘1’) ELSE ‘0’; x <= a OR b OR c; • The order that you write the statements makes no difference, because they are concurrent (working in parallel)

32. VHDL Statements (cont.) • Sequential Statements(means in series) • Sometimes we need to model complex functions. In that case, we can use an “algorithm” or a model to describe the function. This is done with Sequential Statements • With Sequential statements, the ORDER of the statements is important (example later) • Therefore, we use aprocessto mark the beginning and end of a block of sequential statements • Each completed process is considered to be one big concurrent statement (there can be many processes inside one architecture)

33. What is a VHDL “Process” ? • Processes are either awake or asleep (active or inactive) • A process normally has a sensitivity list • When a signal in that sensitivity list changes value, the process wakes up and all of the sequential statements are “executed” • For example, a process with a clock signal in its sensitivity list will become active on changes of the clock signal • At the end of the process, all the outputs are updated and the process goes back to sleep until the next time a signal changes in the sensitivity list

34. The Process: An Example mux: PROCESS (a, b, s) BEGIN IF s = '0' THEN x <= a; ELSE x <= b; END IF; END PROCESS mux; s a(3 DOWNTO 0) x(3 DOWNTO 0) b(3 DOWNTO 0) • The process mux is sensitive to signals a, b, and s. That means that whenever any of those signals changes value, the process wakes up, the sequential statements are executed and the output x is updated • Note 1: The logic could be registered (synchronous) or combinatorial • Note 2: The order of the signals in the sensitivity list is not important

35. Combinatorial Logic using Sequential Statements • We have already looked at some examples of combinatorial logic using Concurrent Statements • Let’s take a look at how to create combinatorial logic with sequential statements...

36. Sequential Statement Examples (1) IF-THEN-ELSE • For example, a 4 to 1 mulitplexer could be described as follows: mux4_1: PROCESS (a, b, c, d, s) BEGIN IF s = “00” THEN x <= a ; ELSIF s = “01” THEN x <= b ; ELSIF s = “10” THEN x <= c ; ELSE x <= d ; END IF; END PROCESS mux4_1 ; • Anytime you want to use IF-THEN-ELSE, then you MUST use a process, because it is a sequential statement

37. How can the order of sequential statements make a difference ? ex1: PROCESS (a, b) BEGIN IF a=‘1’ THEN c<=‘0’;-- if a and b are END IF; -- both ‘1’ then IF b=‘1’ THEN c<=‘1’; -- b has priority END IF; -- so c <= ‘1’; END PROCESS ex1; ex2: PROCESS (a, b) BEGIN IF b=‘1’ THEN c<=‘1’; -- if a and b are END IF; -- both ‘1’ then IF a=‘1’ THEN c<=‘0’;-- a has priority END IF; -- so c <= ‘0’; END PROCESS ex2;

38. Sequential Statement Examples (1) CASE-WHEN • Another way to describe the same 4 to 1 mux: mux4_1: PROCESS (a,b,c,d,s) BEGIN CASE s IS WHEN "00" => x <= a; WHEN "01" => x <= b; WHEN "10” => x <= c; WHEN OTHERS => x <= d; END CASE; END PROCESS mux4_1; • Anytime you want to use CASE-WHEN, then you MUST use a process, because it is a sequential statement

39. c A Note about ProcessesSignal Assignment • Take a look at the following piece of code. Which circuit do you think will be synthesized ? PROCESS (clock) BEGIN IF rising_edge(clock) THEN b <= a; -- after the rising clock edge, a goes to b c <= b; -- after the rising clock edge, b goes to c END IF; END PROCESS ; b c a a OR clock clock

40. Signal Assignment in Processes • Inside processes, signals are not updated immediately. Instead, they are scheduled to be updated • The signals are not actually updated until the END PROCESS statement is reached • Therefore, on the previous slide, two registers will be synthesized (c <= b will be the old b) • In some cases, the use of a concurrent statement outside the process will fix the problem, but this is not always possible • So how else can we fix this problem ?

41. Variables • When a concurrent signal assignment outside the process cannot be used, the previous problem can be avoided using a variable • Variables are like signals, BUT they can only be used inside a PROCESS. They cannot be used to communicate information between processes • Variables can be of any valid VHDL data type • The value assigned to a variable is available immediately • Assignment of variables is done using a colon (:), like this: c := a AND b;

42. Using Variables vs. Signals • Solution using a variable within a process: PROCESS (clock) VARIABLE b : std_logic ; BEGIN IF rising_edge(clock) THEN b := a ; -- this is immediate c <= b ; -- this is scheduled END IF; END PROCESS ; a c clock

43. Native Operators (IEEE-1076) • Logical - defined for type BIT, BIT_VECTOR, BOOLEAN • AND, NAND • OR, NOR • XOR, XNOR • NOT • Relational - defined for types BIT, BIT_VECTOR, INTEGER • = (equal to) • /= (not equal to) • < (less than) • <= (less than or equal to) • > (greater than) • >= (greater than or equal to)

44. Native Operators (continued) • Arithmetic - defined for type INTEGER • + (addition), * (multiplication) • - (subtraction) • Concatenation - defined for STRING • & • A STRING is any sequence of characters • std_logic_vector is an example of a STRING Note: None of these operators were defined to support std_logic or std_logic_vector types because in IEEE-1076, std_logic did not exist yet. How can we fix this problem ?

45. Overloaded Operators • In VHDL, any native operator can be overloaded (means re-defined) to accept any other VHDL type. This is very useful. For example: SIGNAL counter: std_logic_vector(15 DOWNTO 0); counter <= counter + 3; -- the native '+' operator supports integers only, but -- we can overload it to accept std_logic_vectors also • The std_arith package from Cypress defines overloaded logical operators (AND, OR, NOT, etc.,) for the std_logic and std_logic_vector types • To get the compiler to recognize std_logic and to overload the operators you need to add 4 lines to the start your VHDL file: LIBRARY ieee; USE ieee.std_logic_1164.all; -- add the std_logic type LIBRARY cypress; USE cypress.std_arith.all; -- add overloaded operators

46. VHDL Identifiers • Identifiers are any user-defined labels, signal names, port names, entity names etc. VHDL has some restrictions on identifer names: • Letters, digits, and underscores only (first character must be a letter) • The last character cannot be an underscore • Two underscores in succession are not allowed • Using reserved words is not allowed • Examples that are legal: tx_clk, Three_State_Enable, sel7D, HIT_1124 • Examples that are not legal: _tx_clk, 8B10B, large#num, entity, clk_

47. a(0 TO 3) aeqb b(0 TO 3) Exercise #2: Architecture Declaration of a Comparator • The entity declaration is as follows: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY compare ISPORT ( a, b: IN std_logic_vector(0 TO 3); aeqb: OUT std_logic); END compare; • Write an architecture that causes aeqb to be asserted high only when a is equal to b • Multiple solutions exist. Look back at the 4-1 mux examples

48. Ex2 Solution: 3 possible solutions • Concurrent statement solution using a conditional assignment: ARCHITECTURE archcompare OF compare IS BEGIN aeqb <= '1' WHEN a = b ELSE '0'; END archcompare; • Concurrent statement solution using boolean equations: ARCHITECTURE archcompare OF compare IS BEGIN aeqb <= NOT( (a(0) XOR b(0)) OR (a(1) XOR b(1)) OR (a(2) XOR b(2)) OR (a(3) XOR b(3))); END archcompare;

49. a(0 TO 3) aeqb b(0 TO 3) 3 possible solutions (contd.) • Solution using a process with sequential statements: ARCHITECTURE archcompare OF compare IS BEGIN comp: PROCESS (a, b) BEGIN IF a = b THEN aeqb <= '1'; ELSE aeqb <= '0'; END IF; END PROCESS comp; END archcompare;

50. Aggregates and Subscripts • The aggregate assignment joins signals together • Good for creating a bus from several single bits • Concatenation operator can be used as well • Same number of array elements on both sides tmp <= (a,b,c,d); -- called an aggregate tmp <= a & b & c & d; -- concatenation operator • Signals can be extracted from larger vectors • Good for grouping outputs as an “alias” • Sizes on both sides must match rw <= ctrl(0); ce <= ctrl(1); oe <= ctrl(2); highcount <= count(7 DOWNTO 4);