Clock and Synchronization

1. Clock and Synchronization Chapter 16

2. Outline • Why synchronous? • Clock distribution network and skew • Multiple-clock system • Meta-stability and synchronization failure • Synchronizer Chapter 16

3. 1. Why synchronous Chapter 16

4. Timing of a combinational digital system • Steady state • Signal reaches a stable value • Modeled by Boolean algebra • Transient period • Signal may fluctuate • No simple model • Propagation delay: time to reach the steady state Chapter 16

5. Timing Hazards • Hazards: the fluctuation occurring during the transient period • Static hazard: glitch when the signal should be stable • Dynamic hazard: a glitch in transition • Due to the multiple converging paths of an output port Chapter 16

6. E.g., static-hazard (sh=ab’+bc; a=c=1) Chapter 16

7. E.g., dynamic hazard (a=c=d=1) Chapter 16

8. E.g., Hazard of circuit with closed feedback loop (async seq circuit) Chapter 16

9. Chapter 16

10. Dealing with hazards In a small number of cases, additional logic can be added to eliminate race (and hazards). Chapter 16

11. This is not feasible for synthesis • What’s can go wrong: • During logic synthesis, the logic expressions will be rearranged and optimized. • During technology mapping, generic gates will be re-mapped • During placement & routing, wire delays may change • It is bad for testing verification Chapter 16

12. Important Timing Parameters in Flip-Flops Tcq: clock-to-q delay, is the propagation delay required for the d input to show up at the q output after the sampling edge of the clock (rising or falling edge). Tsetup: setup time, the time interval in which the d signal must be stable before the clock edge arrives. Thold: hold time, the time interval in which the d signal must be stable after the clock edge. Chapter 16

13. Better way to handle hazards Ignore glitches in the transient period and retrieve the data after the signal is stabilized In a sequential circuit Use a clock signal to sample the signal and store the stable value in a register. But register introduces new timing constraint (setup time and hold time) Chapter 16

14. Synchronous system: group registers into a single group and drive them with the same clock Timing analysis for a single feedback loop Chapter 16

15. Synchronous circuit and EDA • Synthesis: reduce to combinational circuit synthesis • Timing analysis: involve only a single closed feedback loop (others reduce to combinational circuit analysis) • Simulation: support “cycle-based simulation” • Testing: can facilitate scan-chain Chapter 16

16. 2. Clock distribution network and skew Chapter 16

17. Clock distribution network • Ideal clock: clock’s rising edges arrive at FFs at the same time • Real implementation: • Driving capability of each cell is limited • Need a network of buffers to drive all FFs • In ASIC: done by clock synthesis (a step in physical synthesis) • In FPGA: pre-fabricated clock distribution network Chapter 16

18. Block diagram • Ideal H-routing Chapter 16

19. Clock skew Skew: time difference between two arriving clock edges Chapter 16

20. Timing analysis • Setup time constraint (impact on max clock rate) • Hold time constraint Chapter 16

21. Chapter 16

22. Clock skew actually helps increasing clock rate in this particular case Chapter 16

23. If the clock signal travels from the opposite direction • Normally we have to consider the worst case since • No control on clock routing during synthesis • Multiple feedback paths Chapter 16