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Micro-imaging Application of VCSELs

Micro-imaging Application of VCSELs. Group #11 Karthikraman Samakkulam, Neeta Acharya, Manan Shah. Outline. Project Motivation Advantages of VCSELs Challenges in Design Description of Design Problems Encountered Conclusion. Project Motivation. VCSEL used extensively in communications

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Micro-imaging Application of VCSELs

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  1. Micro-imaging Application of VCSELs Group #11 Karthikraman Samakkulam, Neeta Acharya, Manan Shah

  2. Outline • Project Motivation • Advantages of VCSELs • Challenges in Design • Description of Design • Problems Encountered • Conclusion

  3. Project Motivation • VCSEL used extensively in communications • Any other application? • Application in Micro Imaging • Projector Display • Bar Code Scanning

  4. Benefits of VCSELs • Low divergence circular laser beam • High Resolution for Displays • Inexpensive as manufactured in bulk • Capability of manufacturing dense two dimensional laser arrays

  5. Benefits of VCSELs • Low power Consumption • Durability • Operates at high frequencies (up to GHz) • Life 3-5 years

  6. Description Of VCSEL • Structure of VCSELs Light out Contact DBR Oxide aperture DBR Contact

  7. How small is micro?

  8. Layout of VCSEL Array

  9. Challenges in Design • 64 VCSELs controlled independently • Different current ranges for each device Current at rollover = 27.84mA Threshold Current = 1.92mA

  10. Challenges in Design • Insufficient I/O pins on Microcontroller • Extensive combinational logic required • Microcontroller with sufficient memory • Length of code in compliance with memory • Interface for visual display • High light intensity, damage to eyes

  11. Project Design • Microcontroller : HC-12 Vs FPGA • Familiarity with VHDL • Sufficient available memory on FPGA • FPGA limitations • Only 23 I/O pins available • Converting 16 to 64

  12. Circuit Design Function Generator clock FPGA 2:1 MUX 2:1 MUX MUX Select Groups of 4 VCSELs 74LS194 74LS195 Serial input Parallel Load

  13. Circuit Design • 74LS194 (x16) • 4-Bit Bidirectional Universal Shift Register • Input received from FPGA • Shift Right performed on input bits • Output to 74LS195 • 74LS195 (x16) • 4-Bit Parallel Access Shift Register • Parallel load to outputs • Each 74LS195 controls 4 VCSELs

  14. Circuit Design • 74LS157 (x2) • 2-to-1 Multiplexer • Select input to MUX controlled by FPGA • Select = ‘0’ : Outputs LOW • Select = ‘1’ : Outputs CLOCK • Resistors (x64) • Current limiting circuit • 910Ω

  15. Design Test • 8 Single Packaged VCSELs • Logic test • Verify combinational logic • Checking for delays • Degradation of VCSELs

  16. Before and After Voltage (V) Light Intensity (mW) Current (A)

  17. Problems Encountered • Limitations in designing patterns • Size of VCSEL array • Wiring circuit • Magnification • 5X Lens

  18. Problems Encountered • Keeping VCSEL array flat • Variations in brightness • Non-uniformity of fabrication process • Replaced 910Ω resistor with 470Ω

  19. Conclusion • Successful implementation of 8 patterns • Code length : 90Kb • Memory usage : 63Mb • Frequency used : 8Hz • Voltage (peak-to-peak) : 3.5V • Gates used : 9572 out of 100,000

  20. Recommendations for Future • Keyboard input • Changes in code implementation • Minimize the length of code • Using larger VCSEL arrays

  21. Acknowledgements • Professor Choquette • Spencer Hoke

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