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Wolfgang Kühn II. Physikalisches Institut, Universität Giessen

Helmholtz International Center for FAIR. New Developments for DAQ and Triggering. Wolfgang Kühn II. Physikalisches Institut, Universität Giessen. Outline of talk. PANDA Detector and requirements for data acquisition Compute Node Universal scalable platform for multiple applications

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Wolfgang Kühn II. Physikalisches Institut, Universität Giessen

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  1. Helmholtz International Center for FAIR New Developments for DAQ and Triggering Wolfgang Kühn II. Physikalisches Institut, Universität Giessen

  2. Outline of talk • PANDA Detector and requirements for data acquisition • Compute Node • Universal scalable platform for multiple applications • Applications • Summary and Outlook Wolfgang Kühn

  3. Pellet or cluster-jet target 2T Superconducting solenoid for high pt particles 2Tm Dipole for forward tracks 3 Wolfgang Kühn

  4. Central Tracker Forward Chambers Silicon Microvertex detector 4 Wolfgang Kühn

  5. MuonDetectors Forward RICH Barrel DIRC Barrel TOF Forward TOF 5 Endcap DIRC Wolfgang Kühn

  6. PWO EMC ForwardShashlyk EMC HadronCalorimeter 6 Wolfgang Kühn

  7. Requirements for DAQ and Trigger • Interaction rates up to 20MHz • Typical event sizes 4 - 8 kB. • Raw data rates 40GB/s - 200 GB/s • High flexibility and selectivity • Solution: • Continuously sampling data acquisition • No „hardware triggers“ • Event selection in FPGA processors • Connection via high speed networks • Building blocks • Lots of buffer space • Fast and flexible networks • Powerful processors Wolfgang Kühn

  8. General Purpose Compute Nodes Configurable and scalable hardware platform for multiple applications/ experiments • Capable of High Performance Computing • Large Bandwidth • PANDA est. 40 - 200 GB/s • Continuously Sampling ADCs • Real Time processing (trigger) • Processing of up to 2x10**7 events/s • Flexibility: Reusable • HADES upgrade - BESIII upgrade – Panda DAQ & Trigger • Scalability • Flexible network topology Wolfgang Kühn

  9. Compute Node Features • 5 Virtex4 FX60 FPGA • Large Computer Power • 10 GB DDR2 RAM (2GB per FPGA) • Buffering capabilities • 2 Embedded PowerPC in each FPGA • Slow control • 32Gbit/s Bandwidth • 13x RocketIO to backplane • 5x GBit Ethernet Front Panel • 1x GBit Ethernet Backplane • 8x Optical Links • ATCA Compliant • Manageability Wolfgang Kühn

  10. Compute Node Structure Wolfgang Kühn

  11. ATCA Standard • Advanced Telecomm Computer Architecture • Industry standard (PICMG) • Power ~ 200W/slot • Base Interface (GBit Ethernet) • Full mesh backplane • High Speed differential lines Wolfgang Kühn

  12. Application Example: Ring Search Algorithm • Problem: • Find ring images in RICH detector in the presence of background • Idea: • Exploit correlation with tracking detector (MDC) • Result • Background from electronic noise and other sources strongly suppressed • Thresholds for ring finder can be lowered • Improved efficiency Wolfgang Kühn

  13. Challenges and Opportunities • Status: • First board built • Collaboration with IHEP Beijing • Firmware development has started • Linux GBit Ethernet support implemented • Assemble prototype system (HADES@FAIR) • Single ATCA shelf replaces ~ 10 VME crates • Up to 13 CN + 1 CPU module • Implementation of DAQ and trigger algorithm firmware for: • HADES @ FAIR • Use as a prototype DAQ for PANDA detector tests • Timeline: • 2008/09 Firmware for demonstrator system (HADES) • 2010/11 Algorithm development for PANDA • 2012-14 Construction and commissioning of PANDA DAQ Wolfgang Kühn

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