Overall Project Objective:

1. Presentation #3: Smart Cart 525 IdongesitEbong (1-1)Jenna Fu (1-2)Bowei Gai (1-3)Syed Hussain (1-4)Jonathan Lee (1-5)Design Manager: Myron Kwai Overall Project Objective: Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID) technology while creating a quicker, more convenient shopping experience. Stage III: 2 Feb. 2005 Size estimates/floorplan

2. Status • Design Proposal • Project chosen • Verilog obtained/modified • Architecture Proposal • Behavioral Verilog simulated • Size estimates/floorplanning • Gate-level implementation to be simulated in Verilog • Floorplan and more accurate transistor count • Schematic Design (30% done) • Layout • Simulations

3. Design Decisions • Memory types • Price and coupon lookup table  SRAM (will be updated) • Combined price and coupon lookup into one table, added “control” bit to distinguish between the two • Bit widths • Will input different values at different clock cycles; mux using operation code select line will determine whether the function will be performed or not • Inputting store card for encryption 16 bits at a time (using a counter and muxes) to save bits

4. Design Decisions • Two SBOXes for encryption • 14x7 Carry-Save Multiplier • Convenient to lay out • 14-bit Carry-Select Adder • Even though we aren’t focusing on speed, it would be nice to cut down on delay with so many bits

5. Updated Design Flow Encryption Block

6. Rijndael Encryption Algorithm • Inputs: 32-bit text and 32-bit key • Key expansion • Takes in a 32-bit key, puts it in a state diagram, performs byte substitution and other operations • Add round key • XOR’s the key with its round texts • Transformations • ByteSub • ShiftRow • MixColumn

7. Rijndael Encryption Algorithm ByteSub • Each column is dubbed a word • For our implementation, we only have a 2x2 state matrix http://fp.gladman.plus.com/cryptography_technology/rijndael/aes.spec.311.pdf

8. Rijndael Encryption Algorithm SBOX http://fp.gladman.plus.com/cryptography_technology/rijndael/aes.spec.311.pdf A HUGE ROM

9. Rijndael Encryption Algorithm ShiftRow • Each row except the first one is shifted http://fp.gladman.plus.com/cryptography_technology/rijndael/aes.spec.311.pdf

10. Rijndael Encryption Algorithm MixColumns • Multiply each word by a fixed matrix

11. Rijndael Encryption Algorithm AddRoundKey • XOR round text with round key to get cipher text

12. Rijndael Encryption Algorithm Key Expansion • Takes each word in the previous round key state diagram and performs certain operations • If the word subscript is a multiple of 4 then the word becomes the (previous word shifted down once and byte substituted)^(the previous 4th multiple)^(RCN-1) • Where N=current round and we’re given RC1=2 • RCN-1 is padded with zeros to make its size the length of each word • If the word is not a multiple of 4 then the word becomes (previous round’s corresponding column)^(previous word) • Ex: W4=W0^ByteSub(ShiftDownOne(W3))^(00_00_00_02) • Ex: W5=W1^W4

13. Rijndael Encryption Algorithm Whole Picture

14. Encryption Floorplan

15. Floorplan • Estimated area: • Encryption 37,516 μm2 • Multiplier 14,489 μm2 • Adder 3913 μm2 • SRAM 20,000 μm2 • Logic (muxes, buffers) 15,000 μm2 • Registers (inputs/outputs) 8000 μm2 • Total 98,918 μm2 • Estimated density: • (17,456 transistors)/(98,918 μm2) = .18 transistors/μm2

16. Floorplan

17. Floorplan • Metal directionality:

18. Floorplan • Interconnect • Metal1 & Metal2: Vdd, Gnd, local interconnect • Metal3 & Metal4: Clk, reset, global interconnect

19. Problems & Questions • Most efficient implementation of top-level design • Decided to share inputs since we would have otherwise gone way over the 100-pin limit • Power consumption • Newest implementation of top-level more efficient and saves power by “disabling” other blocks when not needed • Floating point or not??? • Toooooo late

20. Behavioral Verilog Simulation 0 lastPrice= x, finalTotal= x, Encrypted_Datareg=xxxxxxxx, Done=x UPDATING COUPONS AND PRICES 15 lastPrice= x, finalTotal= 0, Encrypted_Datareg=xxxxxxxx, Done=x ADDING ITEMS ================================================= Adding 1000 with price of 500c 245 lastPrice= 500, finalTotal= 0, Encrypted_Datareg=xxxxxxxx, Done=x 255 lastPrice= 500, finalTotal= 500, Encrypted_Datareg=xxxxxxxx, Done=x Adding 1010 with price of 750c 275 lastPrice= 750, finalTotal= 1250, Encrypted_Datareg=xxxxxxxx, Done=x Adding 0000 with price of 900c 295 lastPrice= 900, finalTotal= 2150, Encrypted_Datareg=xxxxxxxx, Done=x REMOVING ITEMS ================================================= Removing 1010 with price of 750c 315 lastPrice= 750, finalTotal= 1400, Encrypted_Datareg=xxxxxxxx, Done=x APPLYING COUPON ================================================= Applying 0000 Coupon of value 20c 335 lastPrice= 20, finalTotal= 1380, Encrypted_Datareg=xxxxxxxx, Done=x PERFORMING CHECKOUT ================================================= Applying Tax of 3 percent 365 lastPrice= 20, finalTotal= 142140, Encrypted_Datareg=xxxxxxxx, Done=x Take 2 decimal places to the left to get answer in cents Take 4 decimal places to the left to get answer in dollars COLLECTING CREDIT CARD INFO ================================================= 420Done 445 lastPrice= 20, finalTotal= 142140, Encrypted_Datareg=xxxxxxxx, Done=0 555 lastPrice= 20, finalTotal= 142140, Encrypted_Datareg=991b8daf, Done=1

21. Structural Verilog Simulations • Encryption ENCRYPTION, STRUCTURAL SIMULATION -> encryption works fine, problems with the counter (done bit). ncverilog: *W,DLCPTH (/afs/ece.cmu.edu/project/sandbox/.vol1/NCSU/local/cdssetup/cds.lib,4): cds.lib Invalid path '/tmp/project' (cds.lib command ignored). DEFINE project /tmp/project/ | ncsim: *W,DLCPTH (/afs/ece.cmu.edu/project/sandbox/.vol1/NCSU/local/cdssetup/cds.lib,4): cds.lib Invalid path '/tmp/project' (cds.lib command ignored). Loading snapshot worklib.testRijndael:v .................... Done ncsim: *W,TCLINT: TCL init scripts not found, check TCL_LIBRARY. ncsim> run 0 clk=0, done=x, text_out=xxxxxxxx 2 clk=1, done=0, text_out=xxxxxxxx 4 clk=0, done=0, text_out=xxxxxxxx 6 clk=1, done=0, text_out=xxxxxxxx 8 clk=0, done=0, text_out=xxxxxxxx 10 clk=1, done=0, text_out=19151b16 12 clk=0, done=0, text_out=19151b16 14 clk=1, done=0, text_out=7bba5cd9 16 clk=0, done=0, text_out=7bba5cd9 18 clk=1, done=0, text_out=dea3dea6 20 clk=0, done=0, text_out=dea3dea6 22 clk=1, done=0, text_out=f7cb2a90 24 clk=0, done=0, text_out=f7cb2a90 26 clk=1, done=0, text_out=e832d2b8 28 clk=0, done=0, text_out=e832d2b8 30 clk=1, done=0, text_out=375ae65c 32 clk=0, done=0, text_out=375ae65c 34 clk=1, done=0, text_out=474b144c 36 clk=0, done=0, text_out=474b144c 38 clk=1, done=0, text_out=5aca9514 40 clk=0, done=0, text_out=5aca9514 42 clk=1, done=0, text_out=653cd653 44 clk=0, done=0, text_out=653cd653 46 clk=1, done=1, text_out=e684a113 48 clk=0, done=1, text_out=e684a113 50 clk=1, done=0, text_out=c908b86d 52 clk=0, done=0, text_out=c908b86d 54 clk=1, done=1, text_out=7b6b290d 56 clk=0, done=1, text_out=7b6b290d Simulation complete via $finish(1) at time 57 NS + 0 ./test.v:32 #53 $finish;

22. Structural Verilog Simulations • Adder and Multiplier vlog testAdder.v run -all # 0A= 0, B= 0, total= 0, Cin=0 # 20A= 1, B= 1, total= 2, Cin=0 # 40A= 534, B= 24, total= 558, Cin=0 # 60A= 534, B= 24, total= 510, Cin=1 # 80A= 1043, B=1021, total= 2064, Cin=0 # 100A= 1043, B=1021, total= 22, Cin=1 # 120A= 1638, B= 127, total= 1765, Cin=0 # 140A= 1638, B= 127, total= 1511, Cin=1 # 160A= 4094, B= 100, total= 4194, Cin=0 # 180A= 2195, B=1011, total= 3206, Cin=0 # 200A= 4996, B= 100, total= 5096, Cin=0 # 220A= 5012, B= 30, total= 5042, Cin=0 # 240A= 5500, B= 999, total= 4501, Cin=1 # 260A= 6000, B= 100, total= 5900, Cin=1 # 280A= 8091, B= 100, total= 8191, Cin=0 # 300A= 7000, B= 100, total= 7100, Cin=0 # 320A= 9000, B= 100, total= 9100, Cin=0 # 340A= 2047, B=1023, total= 3070, Cin=0 # 360A=16383, B=1023, total=15360, Cin=1 vlog testMultiplier.v run -all # 0A=16383, B=127, product=2080641 # 20A= 4094, B=100, product= 409400 # 40A= 4095, B=100, product= 409500 # 60A= 4096, B=110, product= 450560 # 80A= 5000, B=109, product= 545000 # 100A= 5500, B=106, product= 583000 # 120A= 6030, B=107, product= 645210 # 220A= 8000, B=105, product= 840000 # 320A= 7001, B= 99, product= 693099 # 420A= 9000, B=105, product= 945000 # 520A= 0, B= 0, product= 0 # 540A= 1, B= 1, product= 1 # 560A= 534, B= 24, product= 12816

23. Updated Transistor Count • Encryption 7414 • Multiplier 3122 • Adder 936 • SRAM 2560 • Logic (Muxes, buffers) 2524 • Registers (inputs/outputs) 900 • Total 17,456 • Previous 19,820

24. The Real “Floorplan…”

25. Sweet layouts A“butt”ment Metal5 Interconnect