Author: Ioannis Sourdis , Sri Harsha Katamaneni Publisher: IEEE ASAP,2011 Presenter: Jia-Wei Yo

1. Longest prefix Match and Updates in Range Tries Author: Ioannis Sourdis , Sri Harsha Katamaneni Publisher: IEEE ASAP,2011 Presenter: Jia-Wei Yo Date: 2011/11/16

2. Introduction • Basic Range Trie does not support LPM, while updating the data structure in hardware is not simple. • describe a technique for storing and updating prefixes in a Range Trie in order to support LPM; • present the new Range Trie hardware design, prototyped in a Virtex4-60 FPGA, and synthesized for 90-nm ASICs; • measure the memory overhead of supporting LPM in a Range Trie using real Internet routing tables; • extract traces of Internet router updates for a period of 12 months and evaluate the performance of our proposal.

3. *Range Trie(1/4)

4. *Range Trie(2/4)

5. *Range Trie(3/4) Update complexity (a) O(n) (b) O(m) (c) O()

6. *Range Trie(4/4)

7. Range Tries With LPM & incremental Update(1/7) • Range trie structure maintained three field: • the compared address part values, • some control bits for the comparisons • a pointer to the next level • For LPM support we have added • the lengths • the action pointers of the prefixes stored in the node • the action of the corresponding prefix stored at each parent

8. Range Tries With LPM & incremental Update(2/7) lb_up : greater equal than b2 hb_up : lower than d2

9. Range Tries With LPM & incremental Update(3/7) • Check whether the newly inserted prefix is longer than the existing one • Only then the new prefix in inserted in the corresponding entry, by updating its prefix length and action pointer • The prefix is deleted from the entries stored and replaced with the next longer prefix

10. Range Tries With LPM & incremental Update(4/7) Inserting a new prefix bound in a node can be complex since it require to support Range trie optimization employed to reduce the number of address bits per comparison. In hardware would require complex logic and hence slow circuit. Split trie in two part : fixed part , updatable part. =>bounds can be inserted or deleted only at the updatable part of the tree

11. Range Tries With LPM & incremental Update(5/7) • To reduce the complexity of inserting and deleting bounds in the updatable-levels, we apply in the corresponding nodes only Address Alignment. =>store address of length • This reduces the number of bits per comparison in the updatable part and allows all stored addresses to have the same width and hence to simplify updates.

12. Range Tries With LPM & incremental Update(6/7) Range trie ( software ) implementations allow node-split or –merges during inserting and deletion of prefix bounds. =>become balanced tree =>requires to feed-back and update the parent of the splitted/merged node =>stall pipeline for O() cycle per update n : number of leafs m : branching factor in tree

13. Range Tries With LPM & incremental Update(7/7) Range Trie implementation has a limited number of spare tree-levels to support the updatable tree part. =>stall incoming address lookup requests for a few hundreds of cycles =>tree-rebuild : infrequent

14. Hardware Design(1/2)

15. Hardware Design(2/2) => Support one lookup per cycle and update four cycles

16. Experimental Result(1/4)

17. Experimental Result(2/4)

18. Experimental Result(3/4)

19. Experimental Result(4/4)