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MOS Model 11

MOS Model 11. R. van Langevelde, A.J. Scholten and D.B.M. Klaassen Philips Research, The Netherlands MOS-AK Group Meeting’02 XFAB, Erfurt October 21, 2002. Introduction: MOS Model 11. Goals for MOS Model 11 (MM11):. suitable for digital, analog and RF

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MOS Model 11

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  1. MOS Model 11 R. van Langevelde, A.J. Scholten and D.B.M. Klaassen Philips Research, The Netherlands MOS-AK Group Meeting’02 XFAB, Erfurt October 21, 2002

  2. Introduction: MOS Model 11 Goals for MOS Model 11 (MM11): • suitable for digital, analog and RF • suitable for modern/future CMOS processes • physics based • simulation time comparable to MM9 • number of parameters comparable to MM9 • simple parameter extraction

  3. Introduction: MOS Model 11 Model developed for accurate distortion analysis in circuit design: • surface-potential-based model • accurate transition weak  strong inversion • symmetrical • distortion • accurate description of third-order derivatives (i.e. 3I/V3)

  4. Introduction: MOS Model 11 implemented physical effects: • mobility reduction • bias-dependent series resistance • velocity saturation • conductance effects (CLM, DIBL, etc.) • gate leakage current • gate-induced drain leakage • gate depletion • quantum-mechanical effects • bias-dependent overlap capacitances

  5. Introduction: availability of MM11 • public domain • source code in C (including solver) • documentation of model and parameter extraction • http://www.semiconductors.philips.com/Philips_Models • circuit simulators • Pstar (Philips in-house) • Spectre (Cadence) • Hspice (Avant!) • ADS (Agilent) • Eldo (Mentor Graphics) • HSIM (NASSDA)

  6. Introduction: structure of MOS Model 11 W, L Junction diodes modelled by JUNCAP-model Geometry Scaling T Temperature Scaling Model Equations

  7. MOS Model 11: outline • Introduction • DC-Model • AC-Model • Noise Model • Model Parameters & Extraction • Summary

  8. VSB= 0 V VDS = 1 V DC-Model: VT-based model VT-based model: 10 -3 interpolation needed between subthreshold and superthreshold (e.g. BSIM4 and MM9) 10 -4 10 -5 IDS (A) 10 -6 10 -7 10 -8 10 -9 Smoothing function 10 -10 0 1 2 VGS (V)

  9. DC-Model: surface-potential-based model s-based model: 10 -4 I = I + I drift diff DS single equation for whole operation range: 10 -5 I 10 -6 diff 10 -7 IDS (A) Idrift = f(VGB ,s0 ,sL) 10 -8 VSB = 0 V 10 -9 Idiff = g(VGB ,s0 ,sL) VDS = 1 V 10 -10 I drift 10 -11 0 1 2 IDS = Idrift + Idiff VGS (V)

  10. DC-Model: surface potentialys V = VSB at Source V = VDB at Drain Quasi-Fermi Potential V: V VGB EC EF Ei EV Gate Oxide Substrate

  11. time consuming approximation used: s = s(VGB ,V) (Solid-State Electron. 44, 2000) DC-Model: surface potential approximation iterative solution

  12. For real devices several physical effects have to be taken into account: • mobility effects • conductance effects new models Special attention to: • distortion • drain-source symmetry DC-Model: surface-potential-based model Description of ideal long-channel MOSFET

  13. DC-Model: distortion behavior IOUT 1 2 3 Amplitude 4 Harmonic VIN • 2nd-order distortion: cancels out in balanced circuit • 3rd-order distortion:limits dynamic range  accurate description of 3rd-order derivatives

  14. -5 10 HD1 -6 10 -7 10 HD2 Harmonic Amplitude (A) -8 10 V = 0 V -9 10 SB = 0.1 V V DS -10 10 HD3 V T -11 10 Mobility Reduction 1 2 3 4 Symbols Measurements and Lines MOS Model 11 V (V) Series-Resistance GS DC-Model: gate-bias induced distortion Gate-bias induced distortion for NMOS, W/L=10/1m

  15. -3 10 -4 10 -5 10 Harmonic Amplitude (A) 10 -6 10 -7 10 -8 0 1 2 3 4 Channel Length V (V) Modulation DS DC-Model: conductance modeling Drain-bias induced distortion for NMOS W/L=10/1m V = 0 V Static Feedback SB and V = 2.5 V GS Self-Heating HD1 HD2 HD3 Velocity Weak-Avalanche Saturation

  16. DC-Model: RF-distortion modeling RF-distortion determined by DC model f=16 MHz f=1 GHz NMOS, W/L=160/0.35mm, VDS=3.3 V, PIN=-5dBm

  17. Outline: DC-Model • VT vs. s-based models • Distortion modeling • Symmetry • Gate leakage current

  18. MOS models developed for VDS  0 for VDS< 0, source & drain are interchanged In order to preserve symmetry: IDS(VGS , VDS , VSB) = -IDS(VGD , VSD , VDB) Care has to be taken with the implementation of: • ideal current equation • velocity saturation • DIBL/static feedback • smoothing function (linear/saturation region) DC-Model : drain-source symmetry Symmetry w.r.t. source and drain at VDS= 0

  19. Not valid for threshold-voltage-based models MOS Model 9 MOS Model 9 DC-Model : drain-source symmetry IDS(VGS , VDS , VSB) = -IDS(VGD , VSD , VDB)

  20. Care has to be taken to preserve symmetry MOS Model 11 MOS Model 9 MOS Model 9 MOS Model 11 DC-Model : drain-source symmetry IDS(VGS , VDS , VSB) = -IDS(VGD , VSD , VDB)

  21. Outline: DC-Model • VT vs. s-based models • Distortion modeling • Symmetry • Gate leakage current

  22. VGS potential Gate Drain Source bulk DC-Model: gate leakage current

  23. VGS tox JG Gate { Drain Source bulk Simplified relation: where: DC-Model: gate leakage current NMOS, VDS=0V

  24. - EC EF Approximation (at VDS=0 V): Ei EV Gate Oxide Substrate parameters DC-Model: gate leakage model NMOS (in inversion): Gate current density: electron charge density tunnelling probability

  25. VGS>0 IG S D IGS IGD NMOS, tox=2 nm, Area=6 m2 DC-Model: gate current components

  26. VGS>0 IG IGOV IGS IGD S D NMOS, tox=2 nm, Area=6 m2 DC-Model: gate current components

  27. VGS<0 IG IGOV S D IGS IGD NMOS, tox=2 nm, Area=6 m2 DC-Model: gate current components

  28. VGS<<0 IG IGOV S D IGS IGD IGB NMOS, tox=2 nm, Area=6 m2 DC-Model: gate current components

  29. VGS<<0 IG IGOV S D IGS IGD IGB NMOS, tox=2 nm, Area=6 m2 DC-Model: gate current components

  30. determined by intrinsic region determined by overlap region DC-Model: gate leakage model NMOS, tox=2 nm, Area=6 m2

  31. MOS Model 11: outline • Introduction • DC-Model • AC-Model • Noise Model • Model Parameters & Extraction • Summary

  32. n+ + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - n+ n+ - - - p - - - AC-Model: intrinsic charges Intrinsic Capacitances: where i, j =G, S, D or B

  33. gate depletion effect quantum-mechanical effects tox=3.6nm tox=3.6nm tox=3.2nm AC-Model: input capacitance CGG charge model includes: accumulation physical tox=3.2nm PMOS, VDS=0 V, W/L=80*612/2.5mm

  34. AC-Model: symmetry and reciprocity of capacitances VDS=0V symmetry (CiD=CiS) reciprocity (Cij=Cji) CBD-CBS vs. VG CDS-CSD vs. VG

  35. introducing two parameters: kov and VFBov AC-Model: bias-dependent overlap capacitance Gate n+ n+ + + + + + + - - - - - - Source n+ p n+ Bulk Source/Drain Two-terminal MOS-capacitance: accumulation and depletion region included

  36. AC-Model: bias-dependent overlap capacitance PMOS , VDS=0 V , W/L=152*612/0.18mm Short-channel MOSFET, 0.18mm CMOS

  37. MOS Model 11: outline • Introduction • DC-Model • AC-Model • Noise Model • Model Parameters & Extraction • Summary

  38. induced gate noise 1/f noise thermal noise Noise Model: noise types in MOS transistor induced gate noise

  39. PMOS model 0 1 2 3 4 Vgs [Volt] Noise Model: 1/f-noise 10-8 NMOS 10-9 10-10 10-11 0 1 2 3 4 Vgs [Volt] • unified 1/f noise model: BSIM4, MM9 & MM11 • bias dependence verified • geometrical scaling verified (Kwok K. Hung et al., IEEE TED-37 (3), p.654, 1990; ibid. (5), p.1323, 1990)

  40. Old expression (BSIM,MM9) New expression (MM11) Noise Model: thermal noise • thermal noise: where: (F.M. Klaassen & J. Prins , Philips Res. Repts. 22, p.504, 1967)

  41. no hot electron effect needed to describe noise behaviour (A.J. Scholten et al., IEDM Tech. Dig., pp.155-158, 1999) Noise Model: thermal noise (II) 50 Noise Figure (NMOS, W/L=160/0.35mm, VDS=3.3V)

  42. Noise Model: thermal noise (III) 50 noise figure (no noise parameters needed)  verified on 0.35mm, 0.25mm and 0.18mm CMOS (A.J. Scholten et al., IEDM Tech. Dig., pp.155-158, 1999)

  43. MOS Model 11: outline • Introduction • DC-Model • AC-Model • Noise Model • Model Parameters & Extraction • Summary

  44. Parameters: model structure T WL Geometry Scaling Temperature Scaling Model Equations 37 geometry scaling parameters 13 temperature scaling parameters 39 miniset parameters

  45. ko 0.25 0.2 ko (V1/2) Scaling 0.15 Miniset 0.1 0 5 10 15 1/LE (1/m) Parameters: extraction strategy measurements extract miniset for each dut determine temperature scaling determine geometry scaling parameter set example: 0.12m CMOS

  46. Parameters: measurements required measurements per device 1 ID - VGS - curve for various VSB in linear region 2 ID- VDS - and gDS- VDS - curves for various VGS 3 IG- VGS - and IB- VGS - curves for various VDS 4 CGG - VGS - curve at VSB=VDS=0V (optional)

  47. Parameters: extraction outline • Measurements • Miniset extraction • Temperature scaling • Geometry scaling

  48. Parameters: DC miniset effect parameters threshold kO , B subthreshold slope mO flat-band voltage VFB poly depletion kP mobility reduction  , sr , ph , mob series resistance  , R velocity saturation sat conductance  , DIBL , sf , Th impact ionization a1 , a2 , a3 gate current IGINV, BINV, IGACC, BACC, IGOV

  49. Parameters: miniset extraction strategy extraction strategy: 1st-order estimation (optional) flat-band voltage/poly depletion somewhat different strategy for long-channel and short-channel devices (sub)threshold parameters mobility/series-resistance velocity saturation/conductance gate current start with long- channel device impact ionization

  50. doping concentration in polysilicon gate Parameters: miniset extraction of long-channel device Step 1: 1st-order estimation tox NP } 1st-order parameter estimate } { W miniset parameters L

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