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SBS/A1n Fast DAQ

SBS/A1n Fast DAQ. Alexandre Camsonne October 19 th 2012. Outline. Overview Experiments Channel count Module flipping Test stand CODA 3 / Intel CPU Task list Manpower T imeline Conclusions. Overview. Mixed DAQ using VME for GEM readout and Fastbus for other detectors

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SBS/A1n Fast DAQ

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  1. SBS/A1n Fast DAQ Alexandre Camsonne October 19th 2012

  2. Outline • Overview • Experiments • Channel count • Module flipping • Test stand • CODA 3 / Intel CPU • Task list • Manpower • Timeline • Conclusions

  3. Overview • Mixed DAQ using VME for GEM readout and Fastbus for other detectors • Use multiple crates and modules to reduce deadtime

  4. Experimental rates

  5. Channel count

  6. Crate count

  7. Bigbite spectrometer • Bigbite • Standard Hall A equipment spectrometer used for to E02-013 GEn, • Same setup for 12 GeV A1n experiment and 12 GeV GEn andGMn • Shower counter 7x27 blocks • Preshower • 2x27 blocks • 243 blocks total • Analog sum on shower and preshower all modules available and used in previous experiments SuperBigbite DAQ and Electronics Alexandre Camsonne

  8. SuperBigbite Spectrometer Focal Plane Polarimeter setup SuperBigbite DAQ and Electronics Alexandre Camsonne

  9. Module flipping • Send signals to several modules to reduce encoding deadtime from 8 us to (8 us)N • Important when using HCAL trigger : L1 up to 200 KHz • Use ribbon cable with daisy chaining Signal

  10. Module flipping • V1495 programming • Use Compton prescaler as starting point Front End Busy L1A Fast Clear Fastbus modules x N Fast Clear on output Ntrig modulo N Prescale N Busy out L1A on output Ntrig modulo N

  11. Module flipping • V1495 programming • First version working should be good enough to evaluate dead time improvement • Need implement busy logic and fast clear • Want to implement FIFO to store state for readout and TDC output with board status for sync check • Need to check synch and timing resolution

  12. Test stand • 2 Fastbus Crate and PS from Hall B • OSP done • CODA running from • 2 SFI with Intel VME CPU • TS and VME64X crate to be installed • Error on boards • Interference of TI with Fastbus, one bug fixed with new TI ( missing interrupt line ) • Possibly some other issues between SFI and VME TI • Debugging

  13. Intel CPU • Installed Linux operating system on Compact Flash so board can boot stand alone • Readout of Fastbus working • Trigger with old VME TI with SFI working trying new TI to test improvement with event blocking • Develop code for Fastbus readout with new TI • Develop code for module flipping readout • Port MPD code to Intel CPU

  14. MQT • 16 channels per board • Current drawn to be determined • Additional cost of MQT power suppliesmost likely similar to Fastbus PS with FAN about 11 K$

  15. Tasks • Test GAC, ATC board spares • Test SFI spares • V1495 Module flipping programming • Test Intel CPU

  16. Man Power • Alexandre Camsonne • Sergey Abrahamyan • Daniel Kirby • Mark Jones SuperBigbite DAQ and Electronics Alexandre Camsonne

  17. Time line • 2012 • Power MQT • 4 JLAB FADC250 • Test GAC,ATC, SFI • APV25 with CODA • Test module flipping reach 10 KHz with Fastbus • 2013 • New version V1495 • Test module flipping reach 10 KHz with Fastbus with Fast Clear • Small scale setup for testing : trigger + Fastbus + APV25+Module • 2014 • MPD GEM electronics installed on detectors for A1n • Start Gep electronics • Start Hadron Calorimeter Trigger implementation • Digital Trigger electronics test parasitic • 2015 • Run A1n • 2016 • Hadron Calorimeter complete • Full DAQ setup • 2017 • Ready for GEn SuperBigbite DAQ and Electronics Alexandre Camsonne

  18. Conclusion • Test stand in TEDF ready • Basic readout of Fastbus done with Intel CPU • Development of use of CODA 3 VME TI • Module flipping hardware ready : need to write software and study performance. First glance at performance when buffering with TI or TS • Need to develop module flipping with busy and Fast Clear • Major work to make sure of data synchronization • Start work on MQT • Full test of all electronics and spares

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